Zhoujian Wang Email and Phone Number

 Planning & Implementation & Maintenance SOC FPGA used by EDFA projects. Review technical documents. Issues tracing & supporting

1,ASIC/FPGA 设计验证服务

* ASIC/FPGA laboratory prototyping leader Lead the ASIC/FPGA laboratory prototyping task, focus on prototyping planning (schedule, resource...), status tracking and reporting etc. In some special cases, I also take some validation/verification tasks directly, for instance, JESD interface Up to now, there are 1*ASIC and couples of FPGAs which has done in laboratory and these ASIC/FPGA focus on connectivity (CPRI/OBSAI/Ethernet) and DFE (digital front end, UL processed by SHA team and DL by Oulu team).- Lead laboratory-used FPGA creation This FPGA is used for ASIC validation in lab, whose function as the ADC/DAC source/capture. There have 5 people were involved, I took the leader role and one of module RTL implementation directly (the ADC/DAC interface (JESD and parallel)) - Create the laboratory prototyping team, up to 10 team members.The prototyping team is totally new in SHA SoC. I was nominated as the team line manager in Year 2011 and ramped up the prototyping team starting from zero, which including recruitment, lab space/test tools and equipments, competence setup, WOW(way of work) etc. From recruitment point, there are at least 100+ candidates interviewed within 3 years.- People management Objective setting, objective achievement review, performance evaluation, employee annual compensation plan management, competence setting up, team building, cooperation with global teams, recruiting, vendor management, resource allocation, budget control

- Lead OBSAI RTL verification IP (VIP), based on OVM methodology. (Note: This VIP has ported to UVM.)- Lead CPRI RTL verification IP (VIP), based on UVM methodology. At the same time, take the L1

- Lead SDH CC(cross-connection) ASIC RTL implementation(Shanghai) and whole ASIC verification(90nm) This ASIC is still the co-project ASIC with Munich SoC team, and it supports 20G LOCC. From the viewpoint of work split, Shanghai team took parts of RTL design, including SOH/POH processor, MCU interface and the whole RTL verification. The team size (shanghai) is 8 people.My main focus is leading technical relative tasks, e.g module architecture definition and review, RTL implementation and review, verification environment setup and test report generation etc. At the same time, took the MCU interface RTL implementation.Note: this task was continued after NSN SoC (SHA) department built up.- Lead SDH framer ASIC RTL verification(130nm) This ASIC is the first co-project ASIC with Munich SoC team. In this project, I ported the Munich ASIC verification environment to shanghai and trained the local employees, co-operate ASIC verification members to finish the verification task and issue solve, at the same time, took part of verification task.The ASIC is used in MSTP optical transmission product, and it supports Max. 4 * 2.5G STM16(or 16*STM4 or 16*STM1) line interface.

* Product design The main focus is system requirement definition review and function specification definition, FPGA implementation and Hardware system design review.- Owner of SOH/HOPOH processor. This processor multiplexes and distributes the system needed SOH and POH bytes, ex DCC, between MCU unit and line units (cards) by ways of TDM, it includes control logic for on-board accessing also, ex I2C/SPI The used FPGA type is Altera Cyclone, and the clock rate is 155.52MHz with MCU unit and 19.44 MHz with line units.- Owner of SDH 4*STM1 framer. This framer is used in line unit (card) of 2.5G MSTP product, which including the features of SOH monitor/extractor and insertion, AU-4 interpretation and AU-4 generator etc. and some other control logics, e.g I2C/GPIO. The used FPGA type is Altera Cyclone. - Owner of SDH cross-connection FPGA design. This CC is used in MSTP product, it supports the cross-connection capacity of HOCC 15G VC4/AU3 (98*VC4 or 3*32AU3) and LOCC 5G VC3/VC12 (mixed, the Max. capacity is 4*8* *63 VC12). The chip includes functionality of AUPP and AU generator, HOCC, TUPP, LOCC, SNCP and H/LOPOH monitor and insertion. During this implementation, besides of porting the existed blocks, e.g TUPP, my main task is to reduce the logic size by updating the HOCC and re-structure the design of backplane interface.The used FPGA type is Xilinx V4, and the main system clock rate is 155.520MHz, and the HOCC is 311MHz.* New comer trainer for SDH knowledge and its RTL design know-how

- Lead to develop a user-defined SDH transport product This product designed for S1240 switcher, and it includes 2*STM1 optical interface and couples of E1 or 4M interface, depends on the used traffic card.My responsibility is to take part in the system requirement and architecture definition with partner, design the whole line card, including SCH and FPGA implementation on board. - Interface with the transmission department of Shanghai Bell, as an out-sourcing vendor

* Take part in developing a SDH STM1 transport equipment (1U, box), which used in access-network. I am a member of system requirement definition, and the owner of line interface (STM1 block, Framer + TUPP) and FPGA implementation. The FPGA support 6*63 E1 cross-connection.* Take part in developing a multi-type, low-speed interface product, and act as the assistant of R&D director also. This product supports voice, sync-64bit/s, N*64bit/s, RS232 interface etc low-speed application, which based on the time-slot of E1. I am the owner of E1 block and CPLD designer, which distribute/multiplex the N*64K based on configuration.* Field application engineer to install and maintain the field equipment.