A digital leader in a startup company. It requires me of the ability to build up the whole ASIC design flow including SYN/DFT/ATPG/STA/PTPX and also the FPGA testing environment. I defined the system architecture for power delivery system(von Neumann architecture) and coordinated the the digital team with SW and analog members through several projects. 1 project status is in MP with profit margin 20%.

Senior DRAM controller designer, mainly focused on DD3/4 and LPDDR4 series. Performance enhancement(DDR3 & 4), power scenario definition and cost down are my strengths.Years of experience as DE, FE, and BE roles gives me deep understanding of ASIC development flow.