1. CNN graph mapping on ASIP platform (facedetection, vgg16, deepid2, etc)2. ASIP hardware architecture tuning based on profiling data.3. CNN graph mapping tool development and support.4. Customer support.

1. Develop co-simulation framework between RTL and ARM FastModel.2. Tune ARM FastModel for implementation defined parameters.3. Technical leader of test generation team. Develop test templates with IBM Gpro and debug these tests in top-level verification environment.4. Focal point of ARM FastModel and IBM Gpro, responsible for communication with vendors for any technical issues.

Working in IBM Haifa Research Lab (HRL) for CPU verification and test generation technology. Major responsibility:1. ARM architecture modelling. Including instruction, register and address translation system for the latest V8 architecture.2. Genesys-Pro (Gpro) development. Gpro has been a successful CPU test generation tool both in academy and industry for years. And the daily job includs fixing customer reported bugs and also adding new feature such as user-controlled… Show more Working in IBM Haifa Research Lab (HRL) for CPU verification and test generation technology. Major responsibility:1. ARM architecture modelling. Including instruction, register and address translation system for the latest V8 architecture.2. Genesys-Pro (Gpro) development. Gpro has been a successful CPU test generation tool both in academy and industry for years. And the daily job includs fixing customer reported bugs and also adding new feature such as user-controlled directives and testing knowledge which makes Gpro smater. 3. Customer support. Actively participant in customer's high-end CPU design and verification cycle. Including helping review customer's verification plan, knowledge sharing with IBM's experience on high-end CPU verification and also help customer define test scenarios which can hit the bugs on their design with Gpro. Show less

1. Leader of a verification team (4 engineers) on a multi-core SoC (4 PowerPC cores). Finished resource and schedule planning, the overall verification environment setup which is IBM in-house, C++ based verification infrastructure and some challenging work items such as multi-core booting sequence, tool chain setup and cache coherency test with C code.2. Worked in verification of Edram memory controller, with industrial standard verification methodology-UVM. Finished coding of several… Show more 1. Leader of a verification team (4 engineers) on a multi-core SoC (4 PowerPC cores). Finished resource and schedule planning, the overall verification environment setup which is IBM in-house, C++ based verification infrastructure and some challenging work items such as multi-core booting sequence, tool chain setup and cache coherency test with C code.2. Worked in verification of Edram memory controller, with industrial standard verification methodology-UVM. Finished coding of several verification components and also testcase development.3. As key team member, worked in a global design and verification team for IBM server chip. Resposible for verification environment setup, verification component development in C++ and test case development. Also responsible for regression setup and coverage collecting. Show less

Responsible for developing and maintaining the state-of-art FastSpice simulator-Nanosim and XA. Focus on the diagnostic features such as measure, waveform dumping, circuit check, et al.

1. Verification of a superscalar embeded CPU core. Responsible for design and development of test scenarios for BIU (bus interface unit).2. Verification of a DSP core for audio decoding. Responsible for test generation development and test case development.3. Design and verification of an ASIP (application specific insruction-set processor). Responsible for verification framework development and reference model development.