李晓宇 Email and Phone Number

Mix-Signal Circuit design:﹣ Design PLL for USB2 system. Have very rich engineer experiences on Classical CP-PLL and self-bias PLL.﹣ process : GF7, GF28, GF22fdsoi, TSMC10, TSMC16, TSMC28, UMC28, UMC40, INTEL22, SMIC14, SMIC28, SMIC40, etc.﹣ self-bias PLL: there are 3 loops in this PLL, they are: - 1st loop: consists of the vco, feedback divider, pfd , 2 charge pumps , low pass filter, to fulfill phase lock. - 2nd loop: to set the PLL operation points, relax the… Show more Mix-Signal Circuit design:﹣ Design PLL for USB2 system. Have very rich engineer experiences on Classical CP-PLL and self-bias PLL.﹣ process : GF7, GF28, GF22fdsoi, TSMC10, TSMC16, TSMC28, UMC28, UMC40, INTEL22, SMIC14, SMIC28, SMIC40, etc.﹣ self-bias PLL: there are 3 loops in this PLL, they are: - 1st loop: consists of the vco, feedback divider, pfd , 2 charge pumps , low pass filter, to fulfill phase lock. - 2nd loop: to set the PLL operation points, relax the requirement for charge pump output dynamic range. - 3rd loop: duty-cycle correction circuit, to make a 50% duty-cycle output clock. - Write script(Tcl/Perl/Python) to improve team productivityTechnique Sharing Committee member:﹣ Hold the technique sharing meeting regularly;﹣ Choose the technique topic for each meeting and work with the presenter to prepare the PPT and set up demo environment. PLL design team( 3 people) leader:﹣optimize PLL design flow, maintain a golden testbench library;﹣coordinate PLL design resource, track project schedule;﹣help team member to fix technique issues Show less

 Project ：SA××××(Analog CP-PLL, mass production)﹣ Process：TSMC40G﹣ Design bandgap, the output voltage is 1.2V；﹣ Design charge pump under 0.9V, the current is adjustable between 30uA to 480uA with a step of 30uA, the output voltage range is between 0.2V to 0.7V across PVT with little current mismatch (< 0.5%). Project ：Ch××××(ADPLL，taped out and tested, mass production)﹣ Process：TSMC28hpm﹣ Design current mode low voltage reference circuit﹣ Design differential… Show more  Project ：SA××××(Analog CP-PLL, mass production)﹣ Process：TSMC40G﹣ Design bandgap, the output voltage is 1.2V；﹣ Design charge pump under 0.9V, the current is adjustable between 30uA to 480uA with a step of 30uA, the output voltage range is between 0.2V to 0.7V across PVT with little current mismatch (< 0.5%). Project ：Ch××××(ADPLL，taped out and tested, mass production)﹣ Process：TSMC28hpm﹣ Design current mode low voltage reference circuit﹣ Design differential Time to Digital converter(TDC), 7ps resolution @typical﹣ Design Any Rate Divider, which was composed of a Sigma-Delta Modulator with the ability to eliminate truncation error, a multi-modulus divider and a PI (phase interpolator), can realize fractional frequency divide ratio with a resolution of one thirty-second of the input signal’s cycle.﹣ Test results : the PLL’s jitter is better than 300fs(without spur)/600fs(with spur) in the integral bandwidth from 20KHz to 20MHz; Project ：Ch××××(ADPLL, taped out, mass-production)﹣ Process：TSMC28hpm﹣ Design DTC and file relative patents. The DTC improved the PLL’s phase detect resolution to better than 1ps @ TYP corner ﹣ Design LC DCOs. Designed two versions of LC oscillator @7.86GHz, one oscillator utilized a structure with transformer feedback, the other with noise filter, both structures’ phase noise were better than -120dB(@1MHz offset)﹣ Design Any Rate Divider. An injection locked divider provided 8 phases to the divider, the PI generated 16 phases between two adjacent phases, the resolution is 1/128 of the input signal’s cycle Show less