谢晓鹏 Email and Phone Number
Over 17 years work experience of semiconductor technology, include 2years Foundry process engineer and 15 years IC layout design engineerexperience. Always complete the job on schedule, good at solving problems.TSMC 16nm Fin-FET Serdes/Mixed-Signal, 28nm AFE, 28nm Full Custom Digital Layout, 40nm AFE layout work experience.With Totem EM, Voltage Storm, CoolTime, RedHawk IR drop/EM analysisexperience.Mastered Cadence Virtuoso and Laker layout design tools and CadenceDracula, Mentor Calibre LVS/DRC verification tools.Familiar with the semiconductor process, circuit structure, physical design, Tapeout and Maskreview flow, pretty good communication with circuit designer.Analog, Mixed Signal, VDMOS and Full Custom Digital product layoutexperience and ESD protect device layout experience.
Broadcom Limited
View- Website:
- broadcom.com
- Employees:
- 40919
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Senior Ic Layout Design EngineerBroadcom Limited Dec 2008 - Present中国 上海市区Layout design for 16nn Fin-Fet Mixed Signal IP. Layout design and EM analysis for 16nm Fin-Fet SerDes May 2016 shuttle. Layout design for 28nm pcc_ta, azcomp_wrap, abufo, ….. Layout design for 2013 TSMC 16nm FinFET technology shuttle. Layout design and EM and IR drop analysis for 20nm shuttle project in2012.Lead the 28nm custom digital layout team completed acs_64 for Spyderproject in 2011.Layout work and Voltage Storm IR drop/EM analysis for 40nm from2008 to 2010.
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Layout Design EngineerCr Powtech (Shanghai) Co., Ltd. May 2005 - Dec 2008中国 上海Mixed Signal and Analog layout design for the PT1103(RingingCircuit), PT5303/5304 (ClassAB Audio Amplifier), PT5115(Biploar)PT1101(DC-DC), PT1105(DC-DC), PT4101(LED Driver),PT4301(LED Driver).Write the Dracula/Calibre DRC, LVS, LVL command files SinoMOS40V Hight Voltage CMOS Process and CSWC 36V Bipolar Process. Support EDA tools use and maintance include Cadence, Mentor,Synopsys -
Ic Layout Design EngineerAdvance Analog Circuit (Shanghai) Co., Ltd. Aug 2004 - Oct 2005中国 上海Layout design for Bipolar products include Moto Driver / LDO.Write DRC LVS command file for 1.5um Poly Emitter BipolarProcess.
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Layout EngineerXi'An Miroelectronic Institute May 2001 - Aug 2004中国 陕西 西安Layout design Audio Amplifier, 100V/200V/400V VDMOS ,SOI technology Operation Amplifier, SOI technology SignalGenerator.
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Semiconductor Process Engineer吉林华微电子股份有限公司 Jul 1999 - May 2001中国 吉林 吉林Development for Semiconductor Laser, VDMOS processdevelopment, 12V CMOS process development.
谢晓鹏 Education Details
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微电子技术
Frequently Asked Questions about 谢晓鹏
What company does 谢晓鹏 work for?
谢晓鹏 works for Broadcom Limited
What is 谢晓鹏's role at the current company?
谢晓鹏's current role is Broadcom Limited - Senior IC Layout Design Engineer.
What schools did 谢晓鹏 attend?
谢晓鹏 attended 合肥工业大学.
Who are 谢晓鹏's colleagues?
谢晓鹏's colleagues are Zhe Chen, Lei Tian, Steve Tsirlemes, Sathya Poornima Vaddepally, Markus Schwarzfischer, Mitu Patra, Larry Brock.
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