Profile :Over 4 years of IC layout experience, working with both mature and advanced processes .Key Experience:· Advanced process FinFET layout expertise (12nm and 3nm). · Ｍature process layout expertise (12nm, 22nm, 55nm, 90nm, 180nm etc).· Skilled in optimizing post-layout simulations in collaboration with R&D teams.· Primarily worked as a contractor for Novatek Microelectronics Corp. and Marvell Technology, Inc.
雷曜科技
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布局工程師雷曜科技 Mar 2020 - Present新竹地區
Frequently Asked Questions about 張智淵
What company does 張智淵 work for?
張智淵 works for 雷曜科技
What is 張智淵's role at the current company?
張智淵's current role is IC layout engineer 位於 雷曜科技.
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張智淵 attended 明新科技大學.
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