徐柳明 Email & Phone Number

Shanghai

- 2013.3~present- SOC projects(28nm): DFT including scan chain inserting at block level, chain verification, spf test setup procedure generation and pattern generation and verification for both SA and TDF at top level.Test coverage analysis and Test points file generation to improve the test coverage and to reduce pattern number with TMAX tool and manual generation.(test coverage up to 99.5%)- 2009.3~2013.2- Read channal project serial(45nm): DFT including scan chain insertion, atpg pattern generation, convertion and verification.- Fault simulation, estimate the functional test case test coverage through creative circuits around nonscan custom IP(verifault)- - 2008.10~2009.3- Read channal project serial(65nm): Memory Bist. Bist Algorithm selection. Memory group defination. Bist clock plan.- - 2008.2~2008.10- Read channal project serial(65nm): STA, ECO and Timing model extracting.- - 2007.2~2008.2- Read channal project serial(90nm): STA and ECO.

Shanghai

- 2006.6~2007.2- TV Decoder, Architectural definition, synthesis, dft, sta.- - 2005.10~2006.6- AHB2PCI’s bridge in the 32bits SOC. Including architectural definition、rtl coding、synthesis、dft insert、sta. - - 2004.9~2005.9- After successful single mask, I have another two successful single masks for VoIP. And they have been taken to market.- - 2003.10~2004.8- VoIP, responsible for gated clock; In order to minimize the power consumption, because some function is not always active, if it doesn’t work, operating system will remove it’s clock to save power though a control register. After single mask, I am responsible for testing including function and atpg. Now we take this product to market.- 2002.9-2003.09- The network interface portion (either embedded or as part of a NIC) of a file server operating in either a full or half duplex Gigabit Ethernet LAN. responsible for power management; the power management module has two functions.

Shanghai

- 2000.7-2002.8- Join HDTV channel decode chip team; Attend in a advanced studies;