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台灣 Taiwan 新竹市

Low power flow enhancement and methodology development, including UPF/CLP and Primepower analysis.1.UPF implementation.2.Primepower distributed performance test and analysis.3.PrimePower and CLP tool owner.4.PrimePower-RTL and Spyglass power owner.5.RTL and gate level power analysis and reduction.6.Cadence Joules power owner.

新竹地區

RTL to GDSII out flow implementation and development with N4 & N12 from RTLtoGDSout tapeout.1. Frontend : Including physical synthesis, LEC, UPF implmentation, before CTS timing closure and PPA optimization.2. Backend : Including flooplan, routing resource estimation, PV, CTS, STA and Timing closure.

新竹

1.Physical synthesis : Focus on GPU design physical synthesis including power efficiency improvement、review sdc constraint、Prime-power analysis、congestion issue solution in synthesis stage、physical synthesis flow development.2.Timing-ECO by tweaker for routing congestion.3.physical synthesis flow development and debug.4.LEC: debug including not mapped points,extra,abort,NEQ... and give LEC or synthesis constraint to solve LEC issue.5.GPU PPA analysis, optimize and standard lib characteristic analysis.6. UPF implementation and CLP check.7. project experience of advanced node, includingN7/N4/N12 frontend and N12 backend implementation.

新竹地區

1.Being responsible for STA and Timing-eco CAD tool in primetime and tweaker.2. Handle SDC related issue and writing parser to check correctness of SDC format.3.Providing issue support and CAD tool training to the project team and coworking with EDA vendors to solve design flow and tool issues.4.Development of flow in UMC 14nm include primetime-eco and tweaker.5.development of in-house utility by using C/C++ and tcl, eg, in house testing format translation from stil to s100 , clock matrix generator, etc.6.Maintaing IO level testing tool by using C/C++.

碩士, Engineering

Activities and Societies: 電機工程所籃球隊

學士, Engineering

Activities and Societies: 東華大學籃球校隊