Plan the new computation architecture for new features to give competitive products

•Bring a new thought about modulization, improve and standardize the design flow by extracting common logic from DSP module and other control modules to make IP with clear sub-boundary between control and DSP parts; and this shorten the verification and whole-design process. The standard units include MIF (memory interface) architecture design, vertical-scalar and horizontal-scalar control logic;•SOC architecture definition based on OCP/AXI bus for multi-media processing and IP functionality definition with requirement from customer; system integration, inter-connectivity communication and power domain partition; communication between software and hardware team for CPU sub-system design;•Lead and implement the DSP algorithm design and give detailed micro architecture such as vertical scalar, horizontal scalar, horizontal keystone correction for serveal projects;•Conclude all happened and potential abnormal data-path situations, give detail solution, and solid the RTL code for easily instancing, which makes individual IP be strong default-tolerance ability, then makes the whole system very robust when module integration;•Provide new strategy for debugging at IP level when chip tap-out, which benefits the chip validation processing and provides more work-around method to firmware for mass-production;•Implement a SOC’s main-interconnection design with ARTERIS tool and extend the design with multi-level bus matrix to make each separated level with minimum complex of connectivity and power-domain definition;•Implement a Ultra-low power Image Enhanced System (Frame Rate Convert and HDR) based on MIPI interface at display side for mobile device.

•SOC processor's architecture definition based on single and multi-layer AMBA bus for mobile application processor and mobile co-processor; IP's improvement; and system integration (including clock/reset generation, pad share, power domain partition, and test methodology);•Inter-processor communication design for ARM and DSP, which provides mail-box and shared-buffer strategy;•Design of H.264 HW decoder: functionality partition, system integration and bit-stream parser, and implement CAVLD and motion compensation. The key point is designing a specified 32-bit 3 pipe-lined RISC with two hardware accelerators for bit-stream parser and CAVLD; designing the motion compensation with coupled cache module to reduce the main-memory accessing;•Improve the performance of DRAM controller for multi-media processing based on Denali controller;•Real-timer design: which can support different clock switch;•Completed 2 projects’ FPGA validation; and lead a team to implement a FPGA-platform to provide stimulus of video and audio source and sample result from test-chip.

•SOC peripheral verification based on MCS8051;•Enhance standard 8051 to twice the performance with rising and falling edge triggering at same clock frequency;•Design and maintain SDMMC controller; and write an behavioral module for SD device;•Participate in the architecture definition and valuation about the image-enhanced IC for TV display post-processing; which includes noise reduction and color enhancement;•Complete the algorithm about noise reduction, Saturation and Value's enhanced-processing with modified histogram for LED-TV’s post-processing;•Complete Floyd-Dithering algorithm and its verification;•Participating in R&D of Tax-Controller based on ARM7TDMI and complete the modules: AHB SDRAM controller, general AHB-DMAC and APB-RTC and APB-PWM.