王永亮

王永亮 Email and Phone Number

Senior Physical Design Engineer - 芯原 @ 芯原
shanghai, shanghai, china
王永亮's Location
Shanghai, China, China
About 王永亮

王永亮 is a Senior Physical Design Engineer - 芯原 at 芯原.

王永亮's Current Company Details
芯原

芯原

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Senior Physical Design Engineer - 芯原
shanghai, shanghai, china
Website:
verisilicon.com
Employees:
437
王永亮 Work Experience Details
  • 芯原
    Senior Physical Design Engineer
    芯原 Nov 2013 - Present
    Shang Hai
    Physical implementation from RTL synthesis to GDSII tape out. Focus on static timing analysis both on block level and fullchip level.
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  • Cadence
    Product Validation Intern
    Cadence Oct 2012 - Nov 2013
    Shang Hai
    Regression test about Cadence's APR tool EDI.Review various test cases of Encounter's main function, including floorplan, placement ,cts and routing etc.

王永亮 Education Details

  • Anhui University
    Anhui University
    Electronic Circuits And System
  • Anhui University
    Anhui University
    Microelectronics

Frequently Asked Questions about 王永亮

What company does 王永亮 work for?

王永亮 works for 芯原

What is 王永亮's role at the current company?

王永亮's current role is Senior Physical Design Engineer - 芯原.

What schools did 王永亮 attend?

王永亮 attended Anhui University, Anhui University.

Who are 王永亮's colleagues?

王永亮's colleagues are Zheng Xu, Hairun Wang, Ryan Yang, Xiaolong Yue, Lynn Huang, Jun Kim, Yao Lu.

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