CPU functional verification, fault simulation on functional safety project.Formal verification.

Working as verification lead on security engine chip. Major responsibilities include making verification plan, building soc tb, creating testcases in C/asm, etc.

Responsible for SOC verification and module level verification, including testbench setup, creating vip and test cases according to user manuals.Responsible for analog IP modeling with verilog AMS, including model creation and comparing with spice netlist.

Responsible for SOC verification and module level verification, including testbench setup, creating vip and test cases according to user manuals.Responsible for analog IP modeling with verilog AMS, including model creation and comparing with spice netlist.

Responsible for test pattern conversion for J750 platform and supporting product engineer on production testing problems.