Fpga Logic Engineer
Chengdu Xi De Electronic Information Technology Co., Ltd.
Chengdu, Sichuan, China
A burst direct code division multiple access communication link in the project "A military munition self-organizing network"Algorithm architecture:1) Transmitter: The frame header is multiplied by the frame header address code and the data is spread by QPSK modulation and then multiplied by the data address code and then framed, filtered by root raised cosine (4 times interpolation).2) Receiver:Capture: After the root raised cosine filter, the filtered data buffer to the tracking module (a chip corresponds to four symbols), pumping all the way to the capture module, after the relevant part of the sum of the frequency domain to obtain the correlation peak. Estimated frequency offset and peak position, used to capture the correction frequency offset and bit synchronization.Tracking: corrects the address after the frequency offset, correct the phase offset, and then despread (find a chip corresponding to the maximum symbol of the peak as the demodulated data), then demodulation, compared to the bit error rate.Logical implementation:1) capture module: clock tree design, input data to do ping pong processing, FFT and IFFT IP core multiplexing, data interpolation before FFT and IFFT do zero processing. Multiple is enabled clock processing. As well as debugging process plus AGC two board joint adjustment, the data overflow, do fixed processing.2) tracking module: phase compensation loop clock tree design, debugging from vivado debug export data to MatLab analysis. Loop gain control uses the peak-to-peak correlation peak range to estimate the loop gain for the gain in despreading (the signal is too large for despreading to not overflow.) The signal is too small to ensure that the despreading is correctly leading the loop to converge ).
