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EDA Application Engineer7 years experienceResponsibilities1. Parasitic netlist reduction, analysis, comparison tools• Charging the technical support of tools handling parasitic netlist, normally CalibreView, SPF format.• Find the bug and make reproduce input using LPE tools.• Working on customer’s vendor room to support troubleshooting.• Test new version internally to update release note, and feedback to developer.• Provide the script language for customized solution. 2. Spice simulator, Schematic editor, Layout editor tools• Provide technical support to customer.• Training tools for beginners at customer site. (3 days, attended 20 engineers, 5 times every year)• Find bug and make reproduce test case. Report to developer.• Request new features for user-friendly tools, or customer’s request.• Design and analyze the circuit of newest paper to support better technical service.3. Spice Model Library Generator• Provide modeling service for PDK. (TFT, Diode, BSIM, etc)• Training tool guide, model equation.• Provide technical support for tools, script running.• Customize the built-in equation to support the unusual device characteristics using Verilog.4. Maneger of flexlm LicenseSummary of Key Qualification• Ability to handle the various EDA tools from front-end to back-end.• Knowledge of analog circuit.• Strong knowledge of display pixel circuit.• Experience with C-language to make customized solution.• Experience with fabrication of TFTs.• Familiar with handle parasitic netlists.Computer Skills • Experience with tool - Silvaco toolsJivaro (parasitic RLC reductor), VISO (parasitic analyzer), Belledonne (parasitic comparison),Hipex (full chip parasitic extractor), Clever (3D parasitic extractor),Guardian LVS, DRC, Invar (EM/IR simulator), Smartspice (spice simulator), Gateway (schematic editor), Expert (layout), UTMOST4 (spice model generator)TCAD• Python, Perl, Verilog-A• Linux• Microsoft PPT, WORD, EXCEL• SigmaPlot (plotting tool)