TARAN research group - INRIA centre at Rennes University

Energy efficiency has now become one of the main requirements for virtually all computing platforms. Computer architects are however facing new challenges for the next couple of decades, with the most prominent one being the end of CMOS scaling (Moore’s law). Our belief is that the key to sustaining improvements in performance (both speed and energy) is domain-specific computing where all layers of computing, from languages and compilers to runtime and circuit design, must be carefully tailored to specific contexts. In this new age, the processor will be augmented by a bunch of hardware accelerators meant to perform specific tasks in a more efficient way. Our research team focuses on designing accelerators that can prove energy-efficient and fault-tolerant. Our main objective is to promote Domain-Specific Computing that requires the participation of the algorithm designer, the compiler writer, the microarchitect, and the chip designer. This cannot happen through individually working on the different layers discussed above. The unique composition of TARAN allows us to benefit from our expertise spanning multiple layers in the design stack. Research axes Our research directions may be categorized into the following four directions: Hardware Accelerators, Accurate Computing, Resilient Computing, Embracing Emerging Technologies.