Vivek Dhiman Email & Phone Number

Bangalore Urban, Karnataka, India

SOC RTL design and integrationManagaing Team

Bengaluru, Karnataka, India

SOC RTL Design and integrationManaging Team

Bengaluru Area, India

FPGA Prototyping of large ASIC design on Synopsys-HAPS (Multi-FPGA Based prototyping system).

Hillsboro, OR

FPGA Prototyping of large ASIC design on Synopsys-HAPS (Multi-FPGA Based prototyping system), includes RTL Design, partioning large ASIC Design, Timing closure, Ethernet PHY verification on HAPS

Noida Area, India

• Worked for Altera Corporation, UK----
• Worked on Video IP Design/Validation on Altera FPGA's.
• RTL Coding in verilog/system Verilog, Synthesis, STA, Verification, Board bringup, Onchip debugging
• Client interaction
• Team Management

Noida Area, India

Worked on Verilog, System Verilog, VHDL and SDC PARSER

Hyderabad Area, India

Worked on complete FPGA flow which includes RTL Coding, Pre/Post synthesis simulation, Synthesis, P&R and timing

Hyderabad Area, India

Worked for Actel Semiconductor (Microsemi)Worked on complete FPGA flow which includes RTL Coding, Pre/Post synthesis simulation, Synthesis, P&R and timing

Banglore, India

 Responsible for providing RTL Level Power Optimization solutions with Sequence Design-Power Theater

New Delhi Area, India

Key Responsibilities Responsible for providing RTL Simulation, Synthesis, Timing analysis (STA) Verification, FPGA/ASIC Prototyping (HAPS) Consultancy on ALDEC-Active HDL, Riviera, Synplicity-Synplify Pro & More. Responsible to take part In-House design & verification activities.Responsible for providing Presentation and evaluation of product to customer

New Delhi Area, India

Responsible to Perform RTL Coding & verification for assigned project.

B.E. (E & T), Electronics & Telecommunication

Apgd Vlsi Design, Vlsi Design