GLOBAL FOUNDRY AND TECHNOLOGY SUPPLY CHAIN EXECUTIVEAccomplished semiconductor industry leader including 10 years in executive management. Responsible for strategic sourcing, design enablement, tape-out and yield improvement for all Western Digital’s controllers at three global foundries. Extensive experience in 7nm FinFET processes, device engineering, spice modeling, process integration, reliability, and yield. Vast expertise in challenges and reliability assessment for Automotive and Enterprise applications. Recognized by the senior team for providing exceptional leadership in Foundry Management. Chairman of Mixed Signal Working Committee at Global Semiconductor Association

• Spearheaded WDC foundry technology strategy for all flash controllers. Enabled leading-edge process, such as 16nm and 7nm FinFET process in the design and manufacturing of controllers by developing foundry infrastructure.• Spearheaded WDC foundry technology strategy for all flash controllers. Enabled leading-edge process, such as 16nm and 7nm FinFET process in the design and manufacturing of controllers by developing foundry infrastructure.• Minimized supply risks through implementing cost-effective and geographically diverse supply chain by enabling second-tier foundries.• Negotiated large contracts with leading foundries including pricing, wafer supply assurances, yield and RMA criterion for consumer, enterprise and automotive grade applications.• Provided comprehensive technical and reliability expertise to Physical Design, Mixed Signal, and I/O designers to enable fast, robust and first-time success designs. Conducted comprehensive 16nm and 7nm FINFET design and process training.• Pioneered WDC Automotive Process strategy by leveraging customer process while still maintaining very robust and extremely low failure rates parts. • Accelerated time to market by a fast ramp to production. All the tape-outs were first-time success due to meticulous planning and an internally developed, comprehensive checklist.• Significantly reduced wafer cost through negotiation with foundries and improving yields. Attained very high yields on all controllers by driving foundries and product engineers aggressively.• Managed a global team of highly qualified semiconductor experts who support WDC design centers in India and Israel. Built excellent relationships with cross-functional teams across time zones in WDC.• Developed excellent relationship with all the foundries team members. These personal relationships enable excellent technical and priority support from vendors to WDC.

• Designated as the primary technical expert for advanced technologies. Provided in-depth process, device, modeling, yield, quality and reliability, and failure analysis as well as design-related consultation for 0.18um, 0.13um and 90nm CMOS and SRAM processes. Developed Design for Manufacturing (DFM) methodology for Chartered/IBM 90 and 65nm process offerings.• Successfully spearheaded engagement with US customers on IBM & Chartered’s 90nm and 65nm process technologies. Led collaborating effort with Technology Development groups in IBM to earn major design wins from tier-one customers.• Selected to be team leader by corporate executives to compete for the prized contract from nVIDIA and ATI Graphic Devices. Collaborated with customers’ design, engineering and operations teams and was awarded the largest ever contract in company history (1 million units per quarter).• Identified major business, process and IP gaps for winning the design. Proactively led the team to close gaps by working along with sales, EDA partner, technology development, manufacturing, assembly, and test departments.• Developed Marketing Requirement Document for 90nm and 65nm CMOS and Mixed-Signal/RF processes.• Led three senior device and process engineers in the process technology access department. • Recognized by Fabless Semiconductor Association (FSA) for contribution to Process Qualification.• Member of 401k Corporate Management Committee.