Adam Eldredge Email & Phone Number

Mixed signal IC designer that is capable of architecting and designing high performance and flexible PLLs and CDRs

Listed skills include Time Clocks, Clock Tree Synthesis, Clock Distribution, Cdrs, and 3 others.

• 

  Principal Engineer

  Silicon Labs

  Apr 2000 - Present - Austin, Texas Area

  Designed the 10GHz data path, I/O buffers and biasing circuits for a 2.5GHz/10GHz CDR in 0.15um CMOS. (Part numbers: Si5600, Si5100, Si5110)Lead Architecture and Designer for next genration of 10GHz CDR. This CDR has a tri-loop PLL architecture that enabled a jitter transfer bandwidth down to 200Hz while still having a jitter tolerance bandwidth of 6MHz. The part was revA sampled to customers and is still in volume production. (Part numbers: Si5040, Si5041)Lead Architecture and Designer for the Multi-Synth clock chips. Multi-Synth clock chips have the capability to generate multiple non-integer related outputs with a single VCO. These parts were all revA sampled to customers and are still in volume production. (Part numbers: Si5338, Si5350, Si5330, Si5335, Si5351)Lead Architecture and Designer for a high performance general purpose clock chip. The part has the performance (12kHz-20MHz integrated jitter 70fs-rms) to go into wireless base stations. The part is register programmable to target many applications. For example the part can configured to have 1 to 4 PLL clock cleaners with only 1 LC VCO; clock cleaning bandwidth can be programmed from 1mHz to 1MHz with no external loop filter components; PLL architecture can be reconfigured from a single loop to tri-loop depending on application. This part take Multi-Synth to a whole new level by being able to digital control the placement of clock edges with 15fs accuracy. This part was revA sampled to customers and in volume production (part numbers: Si5380, Si5342, Si5344, Si5345, Si5346, Si5347, Si5348)