AeroLeads people directory · profile

Aditya Pawar Email & Phone Number

Sr Silicon Design Engineer at AMD at AMD
Location: Boxborough, Massachusetts, United States 7 work roles 2 schools
1 work email found @amd.com LinkedIn matched
4 data sources Profile completeness 100%

Contact Signals · 1 work email

Work email a****@amd.com
LinkedIn Profile matched
3 free lookups remaining · No credit card
Current company
AMD
Role
Sr Silicon Design Engineer at AMD
Location
Boxborough, Massachusetts, United States
Company size

Who is Aditya Pawar? Overview

A concise factual answer block for searchers comparing this professional profile.

Quick answer

Aditya Pawar is listed as Sr Silicon Design Engineer at AMD at AMD, a company with 44382 employees, based in Boxborough, Massachusetts, United States. AeroLeads shows a work email signal at amd.com and a matched LinkedIn profile for Aditya Pawar.

Aditya Pawar previously worked as Sr Silicon Design Engineer at Amd and CPU Design Verification Engineer at Wave Computing. Aditya Pawar holds Master’S Degree, Electrical And Computer Engineering from Portland State University.

Company email context

Email format at AMD

This section adds company-level context without repeating Aditya Pawar's masked contact details.

{first}.{last}@amd.com
89% confidence

AeroLeads found 1 current-domain work email signal for Aditya Pawar. Compare company email patterns before reaching out.

Profile bio

About Aditya Pawar

Aditya Pawar is a Sr Silicon Design Engineer at AMD at AMD. He possess expertise in security, digital electronics, microsoft office, verilog, vhdl and 21 more skills.

Listed skills include Security, Digital Electronics, Microsoft Office, Verilog, and 22 others.

Current workplace

Aditya Pawar's current company

Company context helps verify the profile and gives searchers a useful next step.

AMD
Amd
Sr Silicon Design Engineer at AMD
Boxborough, MA, US
Website
Employees
44382
AeroLeads page
7 roles

Aditya Pawar work experience

A career timeline built from the work history available for this profile.

Role listed

Amd

Boxborough, MA, US

Sr Silicon Design Engineer

Current
Amd

Santa Clara, California, US

Feb 2020 - Present

Cpu Design Verification Engineer

San Jose, California(CA), US

- Stimulus Generation· Writing Random stimulus using Custom Random code generator and Verification environment for multi-cluster, multi-core CPUconfigurations. Directed stimulus for corner cases bugs found in regression and instruction bring up.· Stimulus is written in Perl which generates assembly file for testing Execution Unit and Inter-thread.

Feb 2019 - Dec 2019

Design Verification Intern

San Jose, California(CA), US

Nov 2018 - Feb 2019

Signal Integrity Intern

San Jose, CA, US

  • 1. Via Modelling:
  • Modeled and simulated the Via transitions on PCBs with thickness up to 40 layers in Ansys HFSS
  • Optimized the via to have minimum discontinuity by looking at TDR and minimize the return loss
  • Modeled SMA connector footprints and optimized the connector launch 2. Serdes Characterization:
  • Evaluation of 56G PAM4 Serdes on channels varying from low loss channels to backplane channels up to 35dB
  • Evaluated the impact of XTALK and temperature on the Serdes performance
Jan 2018 - Nov 2018

Ic Design Intern

Tempe, Arizona, US

- Used SVA(temporal logic assertion-based language) to formally verify FIFO, SAR ADC, ECC blocks with Yosys-SMTBMC.- Completed Logical Equivalence checks of RTL & Netlist of SAR ADC, FIFO, ECC blocks using Yosys Equivalence checker- Designed and Verified Run Length Encoder using SystemVerilog verification environment in ModelSim- Built Cross compiler for.

Aug 2017 - Nov 2017

Graduate Teaching Assistant

Portland, OR, US

Responsibilities:- Designed Lab for students so that students get to know about Educational Engagement Electrical Validation (E3V) board- Helped the students in questions regarding experiment based on E3V board- Graded the lab and Homework

Jan 2017 - Mar 2017
Team & coworkers

Colleagues at AMD

Other employees you can reach at amd.com. View company contacts for 44382 employees →

2 education records

Aditya Pawar education

Master’S Degree, Electrical And Computer Engineering

Portland State University

Bachelor Of Engineering (B.E.), Electronics And Telecommunications

K. J. Somaiya Institute Of Technology
FAQ

Frequently asked questions about Aditya Pawar

Quick answers generated from the profile data available on this page.

What company does Aditya Pawar work for?

Aditya Pawar works for AMD.

What is Aditya Pawar's role at AMD?

Aditya Pawar is listed as Sr Silicon Design Engineer at AMD at AMD.

What is Aditya Pawar's email address?

AeroLeads has found 1 work email signal at @amd.com for Aditya Pawar at AMD.

Where is Aditya Pawar based?

Aditya Pawar is based in Boxborough, Massachusetts, United States while working with AMD.

What companies has Aditya Pawar worked for?

Aditya Pawar has worked for Amd, Wave Computing, Cisco, Analog Rails, and Portland State University.

Who are Aditya Pawar's colleagues at AMD?

Aditya Pawar's colleagues at AMD include Justin Smith, Yan Chen, Evoxr Aal, Neha Pimpalkar, and Jimmy Fnu.

How can I contact Aditya Pawar?

You can use AeroLeads to view verified contact signals for Aditya Pawar at AMD, including work email, phone, and LinkedIn data when available.

What schools did Aditya Pawar attend?

Aditya Pawar holds Master’S Degree, Electrical And Computer Engineering from Portland State University.

What skills is Aditya Pawar known for?

Aditya Pawar is listed with skills including Security, Digital Electronics, Microsoft Office, Verilog, Vhdl, Matlab, Microsoft Excel, and Microsoft Word.

Find 750M verified contacts

Search by job title, company, industry, location, and seniority. Export verified B2B contact data when you need it.