Aditya Pawar Email & Phone Number

Boxborough, Ma, Us

Santa Clara, California, Us

San Jose, California(Ca), Us

- Stimulus Generation· Writing Random stimulus using Custom Random code generator and Verification environment for multi-cluster, multi-core CPUconfigurations. Directed stimulus for corner cases bugs found in regression and instruction bring up.· Stimulus is written in Perl which generates assembly file for testing Execution Unit and Inter-thread communication unit.· Debugging and root cause issues in regression failures from multi-cluster, multi-core and multi-thread CPU Configs. Failuresdebugged are both RTL and stimulus generators.- Coverage Analysis· Generated code coverage report using URG tool to check for toggle, line, conditional etc. to determine if all the possiblescenarios for a given functionality are covered by the test.· Wrote a shell script to use Synopsys URG tool for merging the coverage from coverage regression runs.- Updating test cases for block-level verification of Bus Interface Unit to increase coverage in SystemVerilog Verification Environment.- Completed Introduction to SystemVerilog and UVM Verification Training by Sunburst Design

San Jose, California(Ca), Us

San Jose, Ca, Us

1. Via Modelling:• Modeled and simulated the Via transitions on PCBs with thickness up to 40 layers in Ansys HFSS• Optimized the via to have minimum discontinuity by looking at TDR and minimize the return loss• Modeled SMA connector footprints and optimized the connector launch 2. Serdes Characterization:• Evaluation of 56G PAM4 Serdes on channels varying from low loss channels to backplane channels up to 35dB• Evaluated the impact of XTALK and temperature on the Serdes performance• Good understanding of Transmitter and Receiver Equalization.• Decent understanding of FFE, CTLE and DFE blocks• Slight working knowledge of FEC. Evaluated the Serdes performance based on PreFEC and post FEC BER• Scripting experience in python to sweep the Serdes parameters and control the temperature on thermo-stream 3. Channel Modeling:• Measured the s-parameters (insertion and return loss) of channels and backplane connectors using VNA.• Measured XTALK (NEXT and FEXT) using 16 port VNA up to 50 GHz.• De-embedded the fixture s-parameters from test fixture measurements to obtain the s-parameters of the DUT in Keysight PLTS• Calculated the skew between differential pairs from measured and simulated s-parameters using Keysight ADS tool• Calculated powersum XTALK, Insertion loss fitting and Insertion loss deviation for channel compliance to a specific standard• Experience with using the probe station and the differential microprobes to measure the s-parameters from BGA to connector region 4. Material Extraction:• Extract material properties (DK, DF) from the measured s-parameters using Simbeor tool after de-embedding short trace from longer trace

Tempe, Arizona, Us

- Used SVA(temporal logic assertion-based language) to formally verify FIFO, SAR ADC, ECC blocks with Yosys-SMTBMC.- Completed Logical Equivalence checks of RTL & Netlist of SAR ADC, FIFO, ECC blocks using Yosys Equivalence checker- Designed and Verified Run Length Encoder using SystemVerilog verification environment in ModelSim- Built Cross compiler for RISC V and automated the process for converting the assembly and C program files into hex file using Makefile - Verification of Nanorisc (RISC V processor) using C programs for correct the functionality of registers (ex GPIO registers).

Portland, Or, Us

Responsibilities:- Designed Lab for students so that students get to know about Educational Engagement Electrical Validation (E3V) board- Helped the students in questions regarding experiment based on E3V board- Graded the lab and Homework

Master’S Degree, Electrical And Computer Engineering

Bachelor Of Engineering (B.E.), Electronics And Telecommunications