Ahsan Uddin Email & Phone Number

Boise, Id, Us

Boise, Id, Us

Boise, Idaho, United States

NAND Flash Cell Device Characterization, Reliability Test Flow Definition, Development, Validation and Integration, Reliability Assessment:• Responsible for Reliability Test flow development and Integration in collaboration with global teams.• Perform upcoming 3D NAND memory Reliability Assessment for Qualification following industry standard.• Provide Electrical characterization and Statistical Analysis of volume test data for new product and process evaluation.

Boise, Idaho, United States

1. Developed 3D XPoint Memory array and Cell characterization utilizing ATE Test Data and Bench Analysis2. 3D XPoint CMOS Development: CMOS and Interconnects Yield Assessment derived from in-line defectivity, parametric test data, hands-on electrical and optical characterization, layout analysis and PFA.3. Provided guidance to TD Integration, Process, Product, Design Engineering for process and electrical performance improvement; Test Solutions Engineering for test optimization.4. Part-Lead for EFA and PFA, guided 4 Engineers and 3 Technicians 5. Memory Array and CMOS hard and soft defectivity characterization through cross-temperature Bench Electrical Testing and Optical Microscopy.6. Lead a Team for Feasibility study and Introduction of new Tools for Failure Identification and Analysis in the R&D Fab.7. Lead Cross-functional Teams for Automation of In-line Defectivity Analysis.

Boise, Idaho Area

1. Developed Yield, EFA and PFA methodologies for Micron’s first Charge Trap 3D NAND Technology, and coordinated overall EFA/PFA activities (5 Engineers and 6 Technicians).2. Provided Yield Assessment and Guidance to process integration, product engineering, process development, inline defect inspection and metrology development groups.3. Analysis of Probed wafer and Parametric test data as well as Bench Electrical Characterization of Memory Array, CMOS and Interconnects for failure analysis of both Charge Trap and Floating Gate 3D NAND Technology.4. Failure Identification using photo-emission, thermal-emission, static and dynamic laser scanning techniques along with delving into Circuit Schematic and Layout in collaboration with product and design.5. Transferred Developed Technology from R&D fab to Manufacturing Fab.6. Extensive hands-on experience in failure analysis (Deprocessing, SEM, Dual Beam FIB, etc.) of both Charge Trap and Floating Gate 3D NAND Technology.

Clemson, Sc

Helped in PhD Advisors Lab transfer with CVD Growth, Electrical Testing, Sensor Testing and AFM set-up, and trained graduate students, and performed research work on 2D crystal heterostructures for nano-electronic and sensing applications.

Sc, Usa

• Demonstrated enhancement of graphene electrical transport properties on PLD Boron Nitride compared to SiO2 substrate.• Devised tunable operation of Graphene/Si Schottky diode Sensor.• Developed fabrication processes for graphene field effect transistor (FET), graphene/Si Schottky Diode and graphene electrical test structures such as Hall Bar, TLM patterns, etc. on SiO2, BN, SiC substrates.• Demonstrated Graphene/Si Schottky Diode based multimodal sensing technique utilizing AC Impedance Spectroscopy and simultaneous modeling of the device impedance spectra by electrical equivalent circuit.• Worked as part of the team to build CVD set-up, and optimize CVD graphene growth and transfer process.• Carried out material characterization of graphene using Raman Spectroscopy, AFM, and SEM for defect and other relevant analysis.• Designed and developed fabrication process for suspended graphene Nanoelectromechanical Systems (MEMS/NEMS), and characterized using Amplitude Modulation (AM) heterodyne technique.

In, Usa

• Fabricated and characterized (material and electrical) few layer thin Molybdenum Disulfide (MoS2) FET for logic application, as well as developed MoS2 based Transistor Model and Logic Circuits in Verilog-A.• Carried out high temperature electrical characterization of Enhancement and Depletion-mode InAlN/AlN/GaN (III-Nitrides) HEMT/HFET, and analyzed the variation in subthreshold slope, threshold voltage, transconductance, etc. • Designed, fabricated and characterized Si Schottky Diode, MOSFET, Inverter, and electrical test structures such as Ring Oscillator, TLM pattern, C-V Measurement pad and Hall bar in CMOS process flow.

In, Usa

• Lab Instructor for Electronics-II• Graded homeworks and lab reports

Dhaka, Bangladesh

• Theoretical study on the charge density at AlxGa1-xN/GaN, InxGa1-xN/GaN, and InN/GaN heterostructure interfaces using 1D Poisson/Schrödinger simulator.

Doctor Of Philosophy (Ph.D.) (2012-2015), Electrical Engineering

Activities and Societies: Student Member, IEEE

Master Of Science (M.S.), Electrical Engineering

Master'S Degree, Applied Physics, Electronics And Communication Engineering

Bachelor'S Degree, Applied Physics, Electronics And Communication Engineering