Maging a team which does SERDES development for client in lower nodes . Defining the scope of work, scheduling and resource management for multiple projects in parallel

Managing a team for Serdes development for client organization ..get involved in top level bump and FP planning , scheduling ,resource management for multiple projects

Layout development lead for Serdes sub blocks such as TX,LDO ,Top level integration

Defining physical architecture for world class IO library in 28nm for FC/WB soc designsMaking sure IO library meets all the requirements in terms of ESD /LU by working with central esd teamWorking with SOC team on physical integrations of IO cells into IO ring Developing QC flow to validate IO layouts Technical lead and mentor for junior layout engineersScribe seal/pad/bump/power/ground cells designs

Lead a team of 3 layout engineers to deliver high quality IO library layouts and physical views (LEF,netlist etc)IO library physical architecture definition for different SOC typesWideIO physical architecture exploration for DDR .IO ring development and ESD/ARC closure for IO testchip including physical verification