Ajithkumar Venugopalan Email & Phone Number

PROFESSIONAL SYNOPSIS  20 years of experience in Analog and mixed signal, Power management, Standard cell, IO cell CMOS Layout. Executed different types of Primary responsibilities which involve Architecture development, Floor planning, Placement, Routing and Verification on IP, Library and Chip level layout. Exposure to full cycle of Custom Mask Layout and the ASIC backend design in VLSI.  Exposure to different process nodes and foundries (14nm to 350nm). Good knowledge about deep submicron issues and solutions, DFM and CMOS failure mechanisms like latch-up, EM and ESD. Good Knowledge of Digital, Analog& Mixed Signal Layout and IO Layout design concepts like matching, shielding, power mesh, IR drop & current density requirement etc. In-depth knowledge of Custom Layout and EDA tools. Good knowledge of Cadence SKILL, Shell scripting. Skilled in flow automation, Windows, Solaris and Linux environments.PROJECTS WORKED Data Converter IP’s ADC, DAC PHY Interfaces USB2.0, UHSII, USB1.1 Standard Cell Library development in 14nm, 20nm, 28nm, 90nm and 130nm I/O GPIOs, Mobile DDR IOs Standalone IP’s Temperature sensor, RTC, PLL, BGR Power management chips Memory SRAM, CMOS ROM, FRAM 15+ Custom test chip tape outs.CMOS PROCESS NODE EXPERIANCE INTEL 14nm TSMC 28nm, 40nm, 90nm, 130nm and 180nm FUJITSU 65nm, 90nm, 180nm and 350nm SMIC 90nm GF 20nm and 180nm