Akram Issa Email & Phone Number

A Principal digital ASIC/SoC/FPGA design engineer with over 20 years of digital IC design experience in the latest Deep Submicron DSM technologies starting in 180/130/90/65/40/28/20/7nm using IBM/TSMC/UMC/Samsung technology.

• Working across multiple teams of SoC server CPU structural logic design teams to provide IP solutions including Scalable Coherent Fabrics, Power Management Solutions, Debug Solutions and System Management Utilities.
• Creating Micro-architecture for various blocks, and RTL development using SystemVerilog.
• Write technical product documents to assist our customers with the use of our IP TRM (Technical Reference Manual).
• Estimate power for blocks using EDA tools and create power models.
• Streamline the production, delivery/release and consumption of our IP using Python scripting.

United States

• Working on multiple IP design that includes:
• Micro-architecture design and implementation for SERDES ADPLL in 10nm intel process.
• Micro-architecture design and implementation for MIPI I2C/I3C V1.1 Host controller IP in 22 nm TSMC process.
• HDMI 2.1 transceiver design prototype. 10nm Chip, and low power Google Pixels TPU 5nm design product,
• RTL development for various blocks using System Verilog.
• Worked with architects and logic designers to understand the power requirements and define power specifications/UPF.

San Diego, California, United States

• Participated in the design of multiple SoC design, that included
• Digital SoC micro-architecture design and implementation of next generation 2x2 MIMO 802.11ax Wi-Fi6 devices.
• Completed Micro-architecture and RTL design for Frequency Encoder/Decoder 2x2 PHY design.
• Participated in the design of multiple SoC Network-On-Chip (NoC) architecture to meet the PPA performance.
• Supported Source Synchronous clock implementation, low power design and area management.
• Explored architecture trade-offs in system performance, area, latency, and throughput.

Wilmington, Massachusetts, United States

• Worked as a principal ASIC designer / team lead for mixed signal wireless transceiver products.
• Cartesian RFIC Baseband chip, and high speed 4GSPS ADC/DAC products.
• Successfully completed RTL development and implementation of Digital Signal Processing (DSP) algorithms (CORDIC, NCOs, multi-rate filter FIR/IIR, and Direct Digital Synthesizer DDS) into 2GHz SoC.
• Technical lead for 3+ engineers on digital blocks to be designed, using ASIC tools.
• Developed scripts required to use the synthesis tools and the analysis of the results.
• Developed timing constraints, Clock-Tree constraints, and analyzed timing results from layout.

Cambridge, Ontario, Canada

• Developed several low power/high speed Broadband Satellite Base-band products.
• This included, a single carrier QPSK modem, a GPRS 2.5G Handheld device, OFDM Power line AV Modem, and Digital Pre-distortion DPD for high performance Power Amplifier.
• Completed OFDM Baseband RTL modem design working on Mapper/De-Mapper for 1024 QAM modulator.
• Implemented full DSP functions which included 384/3072-point FFT/IFFT
• Completed efficient DSP RTL algorithm development for CCD imaging technique, and modeling using MATLAB, and C language.
• Written Micro-architecture specifications for various blocks to be developed.

Ottawa, Ontario, Canada

• Working as a member of IC Switching design engineering team to develop 2/8 Gbit Ethernet Switch.
• Working on the Engress engine to develop the TCAM (Ternary Content Addressable Memory) controller.
• Participating in the design reviews and the Marketing Requirement Design (MRD) document.
• Conducting a feasibility study on the size of the module to be designed as well as the best-optimized way to reduce cost and power consumption.
• Writing the technical specification for the ASIC module to be designed
• Implementing the design according to the technical specification using Verilog

Ottawa, Ontario, Canada

• Working as a member of IC design team for the Digital Message Switch (DMS) PowerPC604-to-PCI bridge controller.
• The design of a Line Card controller (ATM/ADSL Multiplexing), using Altera MAX7000 series
• The design of a VIM Interface Card design for a Wireless application, using Xilinx Virtex-II
• The design of a PCI-to-SDRAM Controller, using Xilinx Virtex-I
• Working on ATM UTOPIA level1/2 for OC-12/192 optical transceiver design.
• Implementing the design according to the technical specification using VHDL.

Master Of Science - Ms

Bachelor Of Applied Science - Basc, Electrical, Electronics And Communications Engineering