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Akram Issa is listed as Sr. Director of ASIC IP Design at xwebtechnologies, based in Cairo, Egypt. AeroLeads shows a matched LinkedIn profile for Akram Issa.
Akram Issa previously worked as Sr. Director of IP Design at Xwebtechnologies and Lead SoC Design Engineer at Intel Corporation. Akram Issa holds Master Of Science - Ms from Cairo University.
● A Principal digital ASIC/SoC/FPGA design and micro-architecture engineer with over 20 years of digital IC design experience in the latest Deep Submicron DSM technologies starting in 180/130/90/65/40/28/20/7nm using IBM/TSMC/UMC/Samsung technology. ● Expertise in translating Marketing requirements into products requirements. ● Extensive project management skills, and resources estimations skills. ● Team leadership with strong technical and personal communication skills. ● Understanding customer requirements and mapping existing solutions with state of technology to create an architectural blueprint, and then implementing them in rapid cycles.● Developed multiple Scope of Work (SoW) and generating IP Technical Reference Manuals (TRM).● Extensive technical depth in chip architecture/Micro-Architecture. ● Expertise in SoC Design performance evaluation and optimization w.r.t DSP/CPU implementation ● Successfully completed multiple Chip lead Designs with successful first-time silicon. ● Efficient Digital Signal Processing (DSP) algorithm design and implementation for SoC wireless/IoT and Audio products. ● Low Power Design techniques using IEEE 1801 UPF standard. ● High-speed digital ASIC design up to 3.0 GHz clock frequency. ● Full Chip synthesis and Static Timing Analysis (STA) constraints. ● High-speed bus Interconnect, and memory controller design using standard architecture such as PCI/AMBA/SPI/CAN, DMA, SDRAM, and TCAM memory design. ● Embedded microprocessor Design using ARM7/9, and Cortex M0 to design a Low latency Peripheral Port/Memory utilizing latest Network-On-Chip (NOC) protocol. ● Broad Band modem designs for wireless/wireline applications such as LTE, OFDM, GPRS, and QPSK. ● ATM UTOPIA level-1/2, and Ethernet 8G-bit switching. ● Aerospace and Satellite communication experience. ● Expertise in telecommunication standards such as 3GPP/GPRS/GSM/OFDM/Wi-Max (IEEE 802.11x, 802.16x). ● Result-oriented, Strong attention to details, Self-starter, Creative with strong analytical & problem-solving, details oriented with excellent communication and documentation skills. Quickly build rapport with individuals.
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A Principal digital ASIC/SoC/FPGA design engineer with over 20 years of digital IC design experience in the latest Deep Submicron DSM technologies starting in 180/130/90/65/40/28/20/7nm using IBM/TSMC/UMC/Samsung technology.
● Working across multiple teams of SoC server CPU structural logic design teams to provide IP solutions including Scalable Coherent Fabrics, Power Management Solutions, Debug Solutions and System Management Utilities.● Creating Micro-architecture for various blocks, and RTL development using SystemVerilog.● Write technical product documents to assist our customers with the use of our IP TRM (Technical Reference Manual). ● Estimate power for blocks using EDA tools and create power models.● Streamline the production, delivery/release and consumption of our IP using Python scripting.
United States
● Working on multiple IP design that includes:● Micro-architecture design and implementation for SERDES ADPLL in 10nm intel process.● Micro-architecture design and implementation for MIPI I2C/I3C V1.1 Host controller IP in 22 nm TSMC process.● HDMI 2.1 transceiver design prototype. 10nm Chip, and low power Google Pixels TPU 5nm design product, ● RTL development for various blocks using System Verilog.● Worked with architects and logic designers to understand the power requirements and define power specifications/UPF.● Supported UPF for design/DV/Implementation teams and verified and signoff low power intent using the VCLP tool.● Worked closely with design, DV, implementation team to define low power vectors, generate early and signoff power data using PTPX.● Analyzed power data and worked closely with PD and design team to optimize for low power and improve overall PPA.● Work in cross function team to deliver FPGA prototyping using Xilinx Vivado, and High-level synthesis tools.
San Diego, California, United States
- Participated in the design of multiple SoC design, that included ● Digital SoC micro-architecture design and implementation of next generation 2x2 MIMO 802.11ax Wi-Fi6 devices. ● Completed Micro-architecture and RTL design for Frequency Encoder/Decoder 2x2 PHY design. ● Participated in the design of multiple SoC Network-On-Chip (NoC) architecture to meet the PPA performance. ● Supported Source Synchronous clock implementation, low power design and area management.● Explored architecture trade-offs in system performance, area, latency, and throughput. ● Developed a complete high performance 1GHz AXI/AMBA Traffic Generators in SystemVerilog RTL environment.● Worked closely with the ASIC architecture, and PD team to resolve any issues related to ECO, FV, ● Developed scripts required to use the synthesis tools and the analysis of the results. ● Developed timing constraints, Clock-Tree constraints, and analyzed timing results from layout.
Wilmington, Massachusetts, United States
● Worked as a principal ASIC designer / team lead for mixed signal wireless transceiver products. ● Cartesian RFIC Baseband chip, and high speed 4GSPS ADC/DAC products.● Successfully completed RTL development and implementation of Digital Signal Processing (DSP) algorithms (CORDIC, NCOs, multi-rate filter FIR/IIR, and Direct Digital Synthesizer DDS) into 2GHz SoC. ● Technical lead for 3+ engineers on digital blocks to be designed, using ASIC tools. ● Developed scripts required to use the synthesis tools and the analysis of the results. ● Developed timing constraints, Clock-Tree constraints, and analyzed timing results from layout. ● Oversaw design and development of SoC systems from specification through to production ready phases. ● Interacted with counterparts on Software, System, verification, and Back-End engineering teams to ensure project scope met specifications. Led/Attended and participated in detailed design reviews. ● Planned, aligned and directed efforts of electrical engineering team, creating culture of teamwork to realize goals and objectives.
Cambridge, Ontario, Canada
● Developed several low power/high speed Broadband Satellite Base-band products. ● This included, a single carrier QPSK modem, a GPRS 2.5G Handheld device, OFDM Power line AV Modem, and Digital Pre-distortion DPD for high performance Power Amplifier. ● Completed OFDM Baseband RTL modem design working on Mapper/De-Mapper for 1024 QAM modulator.● Implemented full DSP functions which included 384/3072-point FFT/IFFT ● Completed efficient DSP RTL algorithm development for CCD imaging technique, and modeling using MATLAB, and C language. ● Written Micro-architecture specifications for various blocks to be developed. ● Designed the blocks by utilizing Verilog-HDL. ● Performed and completed functional simulations. ● Synthesized the design and performed/completed STA. ● Prepared for technical reviews and completed product documentation. ● Mentored the junior engineers throughout the development cycle.
Ottawa, Ontario, Canada
● Working as a member of IC Switching design engineering team to develop 2/8 Gbit Ethernet Switch. ● Working on the Engress engine to develop the TCAM (Ternary Content Addressable Memory) controller. ● Participating in the design reviews and the Marketing Requirement Design (MRD) document.● Conducting a feasibility study on the size of the module to be designed as well as the best-optimized way to reduce cost and power consumption.● Writing the technical specification for the ASIC module to be designed● Implementing the design according to the technical specification using Verilog
Ottawa, Ontario, Canada
● Working as a member of IC design team for the Digital Message Switch (DMS) PowerPC604-to-PCI bridge controller.● The design of a Line Card controller (ATM/ADSL Multiplexing), using Altera MAX7000 series ● The design of a VIM Interface Card design for a Wireless application, using Xilinx Virtex-II ● The design of a PCI-to-SDRAM Controller, using Xilinx Virtex-I ● Working on ATM UTOPIA level1/2 for OC-12/192 optical transceiver design.● Implementing the design according to the technical specification using VHDL. ● Conducting a feasibility study on the size of the module to be designed as well as the best-optimized way to reduce cost and power consumption.
Quick answers generated from the profile data available on this page.
Akram Issa works for xwebtechnologies.
Akram Issa is listed as Sr. Director of ASIC IP Design at xwebtechnologies.
Akram Issa is based in Cairo, Egypt while working with xwebtechnologies.
Akram Issa has worked for Xwebtechnologies, Intel Corporation, Wipro, Qualcomm, and Analog Devices.
You can use AeroLeads to view verified contact signals for Akram Issa at xwebtechnologies, including work email, phone, and LinkedIn data when available.
Akram Issa holds Master Of Science - Ms from Cairo University.
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