• Intel3 Technology Node – Currently working as a Physical Design Integration Engineer on the technology readiness for an A0 project for IO Die using 3nm Technology node. Actively contributed on full chip design planning of the IO Die, partitioning and floorplanning while collaborating with multiple customers to understand the SoC physical hierarchy and the data flow across various partitions.• Owner of Ethernet PHY IP – Performed floorplan evaluations to achieve improved placed timing and providing guidance to customers while also supporting DFT Team to develop their flow by providing post-DFT netlist. Also worked on flow evaluation while fixing flow bugs.• Other responsibilities include developing TCL/Perl scripts to help with automation of analysis and providing technical guidance and leadership to junior engineers.

• PCI Gen6/CXL3.0 end point solution for next-gen Xeon processors – Spearheaded an A0 Project for PCIE Gen 6 validation vehicle on TSMC N5 technology node and was responsible for delivering high quality design with RTL2GDSII implementation and verification on multiple partitions with Block level timing convergence (Static Timing Analysis - STA) across all signoff corners and modes, LV/DRC Convergence, ERC (Electrical Rule Check) Convergence as well as FEV and RV analysis leading to a timely tapeout. The max config of Gen6 X16 was successfully demonstrated within a few days of A0 Power-on leading to a significant impact on several major products.• Owner of PCIE x16 Gen 6 IP – Responsible for the synthesis as well as all aspects of Physical Design from RTL Synthesis to GDS including Floorplanning, DFT (Design-for-testability), Clock Tree Synthesis, Place & Route as well as timing ECOs. Co-ordinated with IP & EDA vendors for Design system enablement and Design execution. Performed closure reviews with the PCIE phy IP vendor to ensure clean integration. Proactively questioned and identified potential issues using the vendor checklist and quickly acted on late critical change requests.

• Low Yield Analysis of the EMIB technology platform – Electrical Yield Engineer responsible for the end-of-line electrical test failure analysis of the assembly and the substrate process and identifying key mechanisms that contribute to the ultimate root cause identification and yield improvement. Improved the assembly yield from 60% during technology development to 99% during PRQ certification as owner on several key product families such as Stratix 10 FPGA and Intel 4th Gen Xeon Scalable Processors. • Conducted hands-on lab work, defined data acquisition strategies and data analysis plans, and recommended corrective actions/fixes to internal customers and module stakeholders as well as the test module to improve electrical test yield loss by leveraging the Test results, FA and Characterization data, and performing commonality and waterfall studies.• Expert in Packaging Failure Analysis – Gained knowledge on package Failure Analysis (FA) techniques with certification on multiple advanced electrical Fault Isolation (FI) tools such as 2D X-Ray, TDR, ELITE, IRLC. Experience with sample preparation such as mechanical cross-sectioning, planar grinding, RIE, de-lidding, and Ion-Milling. Also trained on multiple characterization techniques such as Optical Microscopy, SEM, CSAM, and Analytical Techniques. Completed 60 LYA jobs on average per year by using these FA/FI and characterization tools on various products as well as ATVs. • Yield Analysis Mentor and Trainer – Interacting with a team of technicians and providing guidance on a wide variety of FI/FA methods and strategies. Mentoring junior engineers on yield analysis, developing BKMs and training new team members on novel analysis techniques. Also working with external vendors to assess and down-select the latest fault isolation tools to improve failure analysis efficiency on the complex next-generation packages.

Worked at Elidah as an Electrical engineering Intern. Worked on the design and development of Electrical Muscle Stimulation device to treat female Urinary Incontinence. Worked on the PCB Design of Rechargeable Signal generator to generate specific EMS signal to the Electrodes. Prepared BOM for the units, Researched on the battery requirements and contacted battery suppliers regarding the same, testing and power simulations of the PCB board, created mockups for Android and iOS application to control the signal generator, reverse engineering of circuit boards.

Preparing and conducting tutorials for students for software tools like Matlab, OrCAD PSpice, Mentor Graphics and Cadence. Helping out the students and assisting the Professor in conducting Analog Electronics Lab. Also assisting Professor in his research work related to Micro-Assembly Robotic Arm. Apart from these, my responsibilities included grading students' assignments and exams, uploading lecture presentations and other files and mentoring students for the course projects.

• Worked as part of SoC Architecture and Front-end Integration team (Automotive Industry) • Redesigned a protection module and its interface, aiming at new dynamic design and reduction of on-chip memory to half. Optimization achieved at RTL design level with reduction in area by 5% and trade-off in Power Consumption increased by 15% calculated using SpyGlass in line with the automation industry requirements • Optimized a read-mux select line decoding logic to indexed one-hot decoding from loop one-hot decoding with Power Consumption reduction by 61% and Area reduction by 20% as a synthesis result of Synopsys Design Compiler.

D.R.D.O. is India's premier missile facility with thrust on design, development and flight evaluation of various types of Missile Systems for armed forces.Worked on the project Single Axis Control through Dc Servo Motor with Feedback Devices and the use of CNC machines to develop various parts used in a Missile.

ECIL is a Government of India enterprise and is a pioneer in developing various complex electronic products.Worked in the testing facility to test the various control signals given to a submarine operating for controlling oil pipelines deep under the sea and develop a specific action whenever a non-complaint output was generated.