Student Assistant
without many details: I got an offer to work on a slightly different aspect of motor control and took it. Different from my previous experiences this time the focus wasn't on high-level mathematical algorithms running on the hardware, but instead was shifted to low-level communication of that hardware, namely the communication between FPGA and dSPACE. The issue in the beginning was that there was an unintended communication delay which negatively affected the controlling performance. After some work of getting familiarised with how software interacts with hardware on such low-level and many feedback-sessions in Zoom with a person who knew much more about FPGA programming than I did, eventually this issue was resolved and I documented the updated files using LaTeX — something I haven't used before. with more details: using a Simulink file with an HDL-coder addon a bit-pattern was generated and transmitted to dSPACE, after which it was transmitted back to FPGA, thus making a round trip. after this the original and the round-trip signals were outputted to gates of inverter and measured with oscilloscope. the delay between these two signals was too large. skipping several steps in-between, at some point it became apparent that communication logic between FPGA and dSPACE must be changed in HDL. after these changes were done, the communication had no unintended delays anymore.