Switch IP Group management staff member.Switch Data Path design management within IP Group.

Ownership of the development of packets reorder unit IP within a network processor: micro-architecture definition and documentation, design implementation.Leading activity of network processor implementation over FPGA platform for the purpose of pre-silicon verification and SW development.Chip design team member responsible for the implementation of debug scheme, reset & initialization scheme and multiple purpose pins.Team leader in IP group responsible for the implementation of RX and TX switch data path IPs.

Leading activities of acceleration modules implementation for digital signal processing:architecture and micro architecture definition and documentation,hardware design and verification,post silicon validation.Senior Member of the Technical Staff at Freescale Semiconductor Inc.

Definition and implementation of various cache modules for digital signal processing platforms:architecture and micro-architecture definition and documentation,hardware logic design development,backend flow implementation including synthesis, placement and timing analysis.

Designed various ROM, RAM and memory buffer modules up to transistor level.Designed with layout team ROM array physical implementation.Layout checks for implementation optimizations.Circuit modeling for spice simulation.