Associate Member Of Technical Staff
Current1. Synchronizer flop flow* Developed a flow in which clock inputs of synchronizer flops will be driven by the same clock driver* Placed synchronizer flops and clock driver close together through the flow* The flow serves the purpose of preventing metastability condition* Achieved zero clock driver and distance violations by implementing the synchronizer flop flow, as verified through test script analysis. 2. VOLTUS - IR/EM* Performed IR/EM analysis for Dll block* Set up flow and used VCD files for dynamic IR analysis* Designed an efficient power grid structure, which reduced the dynamic IR drop by 38% as measured by voltus* Set up a flow to derive default switching activity using VCD files 3. Block owner of Dll* Experimented with different flavors of NAND cells to find out which variety gives minimum "average rise delay"* Custom placed taps of all delay lines using scripting* Custom placed buffers and performed custom clock tree synthesis using scripting. Script automates the process of buffer insertion at desired locations. It can handle addition of buffers for any length of delay line* Custom CTS achieves uniform rise delays for all taps.* Used Tcl scripting to place taps of delay Line in "n" columns
