Andrew Steele Email & Phone Number

Maidenhead

Working on design of 128Gs/s DAC and ADC's. Design of High Speed Phase Interpolator and Integrated Divider which allows a 16 phase divided down 8G clocks to be generated form a 4 phase 32G master clock. Able to move phase allignment in sub-picosecond steps in relation to the master clock.

Slough, United Kingdom

Working on design of 100Gs/64Gs CMOS DAC. Including sole responsibility for the following projects. High Speed 12 bit 32 phase Multiplexer operating at a clock speeds of 16G. DLL circuit for high speed ADC. Low power data and clock transmission architectures. All projects completed from Initial design to Simulation and Layout

Cirencester

Design cells for RFID system. Including high current Antenna Driver which met tight emissions targets to allow end customer to integrate the final device into a mobile phone.

Swindon, United Kingdom

Designing cells for the next generation of Audio Noise Cancelation.

Design of a 12 channel 100Gbps interface in accordance with SFI-S, SFI5.2 specifications and operating at a maximum clock frequency of 5.5GHz.

Part of the mixed signal design group, my role involved developing circuit cells for a range of low power Zigbee wireless microcontrollers

Developed Smart Power IC’s on the Topfet 0.44u CMOS Platform. These devices are monolithic intelligent Power IC’s designed for the automotive industry.