Ankan Pramanick Email & Phone Number

Sunnyvale, Ca

Contributing to the exciting world of distributed computing cluster performance.

San Jose

Accountable for all software work done at Advantest America’s R&D Center. Advantest Corp. is the world’s premier provider of automated test equipment (ATE) for the global semiconductor industry.• At its peak strength, directly headed an organization of forty software engineers, and guided the work of over 150 other software developers.• Published a research report outlining the recommended strategic directions for global software R&D at Advantest in the coming years… Show more Accountable for all software work done at Advantest America’s R&D Center. Advantest Corp. is the world’s premier provider of automated test equipment (ATE) for the global semiconductor industry.• At its peak strength, directly headed an organization of forty software engineers, and guided the work of over 150 other software developers.• Published a research report outlining the recommended strategic directions for global software R&D at Advantest in the coming years, identifying and describing the main measures to meet future challenges.• Launched software research projects focusing on exploiting parallel processing to improve the performance of ATE (using, for example, OpenMP); using the capabilities of GPGPUs and their programming models (e.g., CUDA vs. OpenCL); and creating mechanisms to diagnose software problems at the customer site, by dynamic load-time instrumentation of existing runtime libraries, using debug hooking technologies. Show less

Santa Clara

Created and led the core team entrusted with the specification, architecture, design and implementation of the tester operating system and system software products for Advantest’s current-generation test system, the T2000. This was a completely new design, built from the ground up, with the goal of providing the first open architecture system for ATE (Languages: C/C++/C#; platforms: Windows/Linux; environments: Visual C++/GNU tools).• Led the software team through multiple releases of… Show more Created and led the core team entrusted with the specification, architecture, design and implementation of the tester operating system and system software products for Advantest’s current-generation test system, the T2000. This was a completely new design, built from the ground up, with the goal of providing the first open architecture system for ATE (Languages: C/C++/C#; platforms: Windows/Linux; environments: Visual C++/GNU tools).• Led the software team through multiple releases of this product, which has reached record sales (in the billion USD range) over its (continuing) lifespan of a decade, making it one of the most successful product in the history of Advantest, with sales all over the world. The system OS runs on a multi-computer, modular, distributed, re-configurable system, with open user and vendor SDKs.• Restructured Advantest’s software development organizations to clarify roles, responsibilities and accountabilities and increase productivity, in order to deal with the large scale software development project for the T2000 product. Identified gaps in capabilities, and recruited key senior personnel to close the gaps.• Worked with the principal customers to define and specify the system software, and with the Semiconductor Test Consortium (STC) to define the open architecture interfaces and the OpenSTAR specification, the first of its kind in the entire ATE industry.• Established and created the entire software development infrastructure.• Managed IP activities for the T2000 software product, including patent strategy formulation, authoring of invention disclosures, and technology roadmap planning.• Mentored and trained the software group leaders and technical leads who, over time, took up key positions in the T2000 software development organization, both in the US, and in Japan and Germany.• Defined, negotiated and managed interactions with industry partners to establish joint efforts to enhance “direct EDA-to-test” offerings. Show less

Santa Clara, California

Led the engineering group entrusted with delivering the software system for the first event-based tester from Advantest, CertiMAX, based on the DTS prototype (see below).• The system provided a direct link from design simulation to testing. The resultant reduction in validation time and cost (compared with traditional methodologies) amounted to 90%, depending on the design (Languages: C/C++/Java/Tcl-Tk; platforms: Windows/Solaris).• Led the project for the integration of the… Show more Led the engineering group entrusted with delivering the software system for the first event-based tester from Advantest, CertiMAX, based on the DTS prototype (see below).• The system provided a direct link from design simulation to testing. The resultant reduction in validation time and cost (compared with traditional methodologies) amounted to 90%, depending on the design (Languages: C/C++/Java/Tcl-Tk; platforms: Windows/Solaris).• Led the project for the integration of the CertiMAX system with Model Technology Inc. (MTI)’s ModelSim SE mixed-language VHDL/Verilog simulator. This was a collaborative effort between MTI and Advantest to provide a seamless engineering design automation (EDA)-to-test path for mutual customers. (Languages: Java/Tcl-Tk/C++) Show less

Santa Clara, California

Led the software team working on the “middleware” for Advantest’s first, experimental, event-based tester prototype aimed at the design/verification market, the Design Test Station (DTS). • Designed and implemented the "middleware" layers of software for the DTS system, a foundational class library of core classes (named Advantest Foundation Classes), and a communications library. These were later used in other projects (Languages: C/C++/Java; platforms:… Show more Led the software team working on the “middleware” for Advantest’s first, experimental, event-based tester prototype aimed at the design/verification market, the Design Test Station (DTS). • Designed and implemented the "middleware" layers of software for the DTS system, a foundational class library of core classes (named Advantest Foundation Classes), and a communications library. These were later used in other projects (Languages: C/C++/Java; platforms: Windows/Solaris).• Specified and designed the SECS HSMS-based protocol for communicating messages from a remote browser-based control application (using Java applets) to the server, which extracted information from the messages to create worker objects (in C++) on the fly.• Created a framework for lex/yacc-based parser generators to allow for the use of a C++ scanner class object to perform the lexical analysis from within yacc-generated code, to support the passing of optional parameters to the main parsing routine generated by yacc, and to improve on the poor native error reporting in yacc-generated code, by using information from the internal state of the parse table when an error state was encountered. This framework, refined over the years, is used in every major software project within Advantest that uses lex/yacc-based parsers. Show less

Santa Clara, California

Worked on the research and development of Advantest’s next generation software tools aimed at bridging the gap between the EDA and tester worlds. (Languages: C/C++; environment: Windows, Solaris)• Specified, designed and implemented the StilReader product, a cross-platform test program/data translator. This is used to translate from industry-standard simulation formats such as VCD and WGL, and from the IEEE Standard Test Interface Language (STIL), into various vendor- and test… Show more Worked on the research and development of Advantest’s next generation software tools aimed at bridging the gap between the EDA and tester worlds. (Languages: C/C++; environment: Windows, Solaris)• Specified, designed and implemented the StilReader product, a cross-platform test program/data translator. This is used to translate from industry-standard simulation formats such as VCD and WGL, and from the IEEE Standard Test Interface Language (STIL), into various vendor- and test platform-specific formats. StilReader is still being maintained, enhanced, and sold (Languages: C/C++; platforms: Windows/SunOS/Solaris).• Used Rational Rose as the modeling tool for the STILREADER components, and developed the internal flow and rules for managing full round-trip engineering.• Implemented the cross-platform (Solaris and Windows) build and regression test system for the above, to serve a common, shared code-base. This included the automatic generation of Unix makefiles from the main MSVC-based development environment. Also implemented the unit-test framework for the StilReader components. Show less

San Jose, California

Worked on the research and development of Nextwave’s statistical spread-delay Verilog-compatible timing simulator package, EPILOG-MX.• Designed and implemented an improved and more efficient device and interconnect correlation computation and propagation scheme for EPILOG-MX. This scheme minimized spread-delay simulation pessimism by properly handling ambiguity regions. It also produced the useful side-effect of design-debug assisting “trace-back” that was then displayed through… Show more Worked on the research and development of Nextwave’s statistical spread-delay Verilog-compatible timing simulator package, EPILOG-MX.• Designed and implemented an improved and more efficient device and interconnect correlation computation and propagation scheme for EPILOG-MX. This scheme minimized spread-delay simulation pessimism by properly handling ambiguity regions. It also produced the useful side-effect of design-debug assisting “trace-back” that was then displayed through Nextwave’s graphical design debugger, NEXTVIEW. (Language: C; environment: SunOS, Solaris, HP-UX, AIX)• Worked on performance enhancements for the EPILOG-MX simulation engine; the efforts resulted in speed-ups of up to 4 times over the previous product release.• Specified, designed and implemented register identification schemes and a register-plane to register-plane delay mode application for the Nextwave timing analysis tool FOCUS. (Language: C; environment: SunOS, Solaris, HP-UX, AIX)• Designed and implemented an X/Motif based full-featured file browser, FILESCAPE, for Nextwave customer use. (Language: C; environment: SunOS, Solaris, HP-UX, AIX)• Specified, designed and implemented the interface, called Epilog Custom Timing Interface, to Synopsys Logic Modeling Group’s SMARTMODELS library products, so as to integrate customers’ SmartModels into the EPILOG-MX simulation flow. (Languages: Perl and C; environment: SunOS, Solaris, HP-UX, AIX) Show less

New York

Led software development projects addressing logic verification for VLSI designs, design system synchronization for a networked, multi-site VLSI design environment, and IDDq testing and simulation tools.• Conducted research and development for a hierarchical simulation-based logic verification system for VLSI circuits. This addressed a critical need to deal with extremely large designs, including very large custom CMOS arrays. (Language: C; environment: AIX.)• Conducted… Show more Led software development projects addressing logic verification for VLSI designs, design system synchronization for a networked, multi-site VLSI design environment, and IDDq testing and simulation tools.• Conducted research and development for a hierarchical simulation-based logic verification system for VLSI circuits. This addressed a critical need to deal with extremely large designs, including very large custom CMOS arrays. (Language: C; environment: AIX.)• Conducted investigation of a system to simulate CMOS leakage and bridging faults for use with IDDq testing. This was used to choose appropriate vectors for “good” IDDq testing, and obtain coverage estimates under different leakage/bridging fault models, with further applications to testing for faults extracted from physical layout characteristics. (Language: C/C++; environment: AIX, SunOS.) Show less

New York

Participated in software development projects addressing testability issues in logic synthesis, delay fault testing/simulation and fault-coverage enhancement tools, X-Windows/Motif based implementations for physical design tools, development of a code release system for the IBM Mid-Hudson Valley Labs, and CAD tools integration for the Cadence Design System environment.• Worked on efficient Redundancy Identification and Removal (RIR) techniques for synthesis applications, and implemented… Show more Participated in software development projects addressing testability issues in logic synthesis, delay fault testing/simulation and fault-coverage enhancement tools, X-Windows/Motif based implementations for physical design tools, development of a code release system for the IBM Mid-Hudson Valley Labs, and CAD tools integration for the Cadence Design System environment.• Worked on efficient Redundancy Identification and Removal (RIR) techniques for synthesis applications, and implemented an automatic RIR tool for modular-level applications in IBM’s logic synthesis system.• Developed and implemented a parallel gate delay fault simulator and coverage estimator; extended it to a distributed, networked version (Language: C; environments: P4 on DYNIX, PVM on AIX).• Co-invented a scan-based system for sequential circuit design that guaranteed 100% robust delay fault testability, and a new class of testability-preserving transformations for use in optimization stages during logic synthesis.• Developed and implemented a X-Windows/Motif based interactive graphical tool, XPMASK, to aid in early floor-planning and wiring-rows allocation. (Language: C; environment: AIX.).• Taught two-day classes on the Perl programming language at the IBM Mid-Hudson Valley Design Labs. Show less

Bachelor Of Technology (B.Tech.), Electrical Engineering

Doctor Of Philosophy (Ph.D.), Electrical And Computer Engineering

Icse, High School/Secondary Diplomas And Certificates, 11