Anqi has worked as an ASIC design and verification engineer in a startup company in U.S. for 2 years, with 1 ASIC IP successfully delivered and tapeout, with 2 years of experience in all aspects of digital front-end design and scratch up testbench development with SystemVerilog and UVM, also with focus on technologies for high speed interfaces, SSD and memory including PCIe, SATA, Ethernet, NVMe, DDR, SDRAM, NAND flash memory and implementation of DSP algorithms in ASIC/FPGA, especially for Audio and Wireless applications. - Extensive everyday hands-on experience in ASIC/FPGA Design including RTL coding, Synthesis, STA, Timing Closure.- Highly proficient in SystemVerilog, C/C++, UVM, test suites with constrained-random verification, code/functional coverage analysis, SystemVerilog Assertions, Formal Verification, gate level simulation and system modeling.- Hands-on experience in high speed interfaces like PCIe, SATA, Ethernet, USB and SSD controller, NAND Flash memory and DDR SDRAM.- Extensive working experience in design and implementation of DSP algorithms and digital filters in ASIC/FPGA such as FFT, FIR/IIR filter, Adaptive Filtering, Audio CODEC(ADC/DAC), etc.- Experience in Audio signal processing, Acoustic Echo Cancellation, Noise Reduction.- Experience in wireless communication design like channel equalization, interference cancellation, OFDM, LTE, WIFI, array processing for MIMO.- Expertise in ARM based SoC design and verification and diverse types of 8/16/32 bits microcontrollers like ARM, AVR, TI, PIC32, etc.- Strong knowledge of transistor-level circuit design, analog mixed-signal IC design and Computer Architecture.Protocols: Ethernet, USB, PCIe, SATA, UART, I2C, I2S, SPI, TCP/IP, UDP, etc.Languages: Verilog, VHDL, SystemVerilog, C/C++, Perl, TCL, SystemC.Tools: Design Compiler, Prime Time, VCS, Formality, UNIX/Linux, Xilinx ISE, Modelsim, MATLAB, Oscilloscope, Spectrum Analyzer, Logic Analyzer, etc.CONTACT: anqiwang1616@163.com