Enthusiastic and fun-loving circuit enthusiast with a passion for SRAM memory circuit design. A dedicated planter and advocate for green environments. Combining technical prowess with a yogic mindset, I strive to create innovative solutions while supporting a sustainable future. I am keen to learn more about design architectures to improve circuit performance & functionalities. Presently working on self-timed SRAM memories,• Have 6+ years of Industry experience• Analyzed various FOM’s of 6T bit-cell for robust memory design across different PVT’s • Worked on Memory Characterization flows of timing, power & leakage.• Exposed to Memory architecture with various circuit enhancement assist circuitry (Read assist circuit, Write assist circuit) & critical path modelling.• Significant Exposure to validation of the characterized data & timings of memory compliers.• Worked on Run-time reduction for various validation activities with the help of Simulator features (tool).