Arjun Shetty Email & Phone Number

Bengaluru, Karnataka, India

SOC synthesis, Constraints, Timing Analysis, SOC IO interface timing

Bangalore

SOC Synthesis, Constraints, Timing analysis, SOC IO interfaces timing

Bengaluru Urban, Karnataka, India

Hardmacro RTL to synthesis to gds for digital components of analog blocks like SAR ADCs, DACS etc for auto and industrial socs. Test chip level rtl integration of analog test blocks, synthesis, formal equivalence, constraints, timing analysis, gds, physical checks and tapeout.

Bangalore

SOC synthesis, lec, constraints, timing analysis for auto safety chips

Bangalore

Working For Texas Instruments Houston, Automotive group for RTL Integration, IP design, Synthesis, SOC constraints, STA.