I have worked on CMOS RFICs, particularly RF transceiver modules and codesigns with on-chip antennas. I am trained in RFIC design using Cadence tools, for schematic analysis, layout design, parasitic extractions, and post-layout simulations. Additionally, I am also good at EM simulation tools like HFSS, CST, and ADS. I have taped out five chips so far using TSMC 180 nm and SCL 180 nm CMOS technologies.