Self-motivated electrical engineer with a strong academic and research expertise in FPGA/SoC-based design and verification for power grid digitalisation and cybersecurity. Experienced in designing and verifying ADC IP, FIR Filter IP, GPS Timestamping IP, IEC61850 Sampled Values IP, Ethernet MAC IP, FPU, State-estimation based Power system protection relay IP, and False Data Injection Attack Detection IP. Proficient in FPGA development tools (Vivado, Questa), skilled in HDL programming (Verilog/VHDL), and experienced in design verification using System Verilog (UVM, Assertions, Functional Coverage). Proven ability to deliver innovative solutions, collaborate with cross-functional teams, and drive projects from concept to completion.