Ashwin Harikumar Nair Email and Phone Number
Ashwin Harikumar Nair work email
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Ashwin Harikumar Nair personal email
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Analog/Mixed Signal Designer with over 9 years of experience at Intel2019- Now -> Multi GBps clocking circuits for DDR5/LP5 PHY for Intel System-on-Chip (SoC) products.2015-19 -> PLLs/Current Reference generators for intel Atom Cores/5G Modem MPHY2013-15 -> MS Analog Circuits ASU, Intern at High Speed IO Lab Intel (SATA 6G)Hands on Experience with - High Speed Clock Reception, DLL, Distribution, Duty Cycle Correction/Detection, Data path design, Serializers, Clock Splitters, Clock Crossing Circuits, Equalizers and Digital Calibration Loops/FSMsEntire Analog/Mixed Signal Design flow - variation, EMIR analysis, Aging, Mixed Signal Timing - with multiple successful tape out experience on sub 10nm CMOS Finfet (TSMC)
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Senior Analog Soc DesignerIntel Corporation Jul 2019 - PresentSanta Clara, California, UsMulti GigaBit - High Speed Clock Distribution, Duty Cycle Detectors, Phase Detectors/Alignment circuits.Clock Drivers, Differential Clock Receivers, SerializersData Path Design, DDR Receive and Transmit Clocking Mixed Signal Timing AnalysisJitter Link Modelling -
Analog Design EngineerIntel Corporation Jun 2015 - Jul 2019Santa Clara, California, UsIntel 5G Modem Baseband PHY Design.Basedband Receiver Iref design for mPHY : Designed a transistor-level current reference to ensure consistent voltage swing across PVT for the Baseband Receiver.Digital PLL/VCO Simulations for Atom CPU: Conducted DCD simulations for the PLL clock path, optimizing distortion through circuit and layout improvements.
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Graduate Intern : High Speed Interfaces LabIntel Corporation Sep 2014 - Jun 2015Santa Clara, California, UsPost silicon validation on SATA 6G.Developed ATE to automate the compliance validation for SATA 6G interfaces on Intel process nodes catering to IOT products
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Graduate Research StudentArizona State University Dec 2013 - May 2014Tempe, Az, UsStudent researcher working on reconfigurable solar arrays with GaN power switches to improve efficiency of solar arrays using MPPT. Modelled the system using Matlab/Simulink models to perform architecture studies. -
Research Member : Battery Management CircuitsMahindra Electric Vehicles Pvt Ltd Aug 2011 - Apr 2013Research member working towards improvement of battery management algorithims/system for electric vehicles.
Ashwin Harikumar Nair Skills
Ashwin Harikumar Nair Education Details
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Arizona State UniversityElectrical Engineering -
National Institute Of Technology CalicutElectronics And Communications Engineering
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Arizona State UniversityElectrical And Electronics Engineering
Frequently Asked Questions about Ashwin Harikumar Nair
What company does Ashwin Harikumar Nair work for?
Ashwin Harikumar Nair works for Intel Corporation
What is Ashwin Harikumar Nair's role at the current company?
Ashwin Harikumar Nair's current role is Analog/Mixed Signal IC Design | DDR | Clocking.
What is Ashwin Harikumar Nair's email address?
Ashwin Harikumar Nair's email address is as****@****ail.com
What schools did Ashwin Harikumar Nair attend?
Ashwin Harikumar Nair attended Arizona State University, National Institute Of Technology Calicut, Arizona State University.
What are some of Ashwin Harikumar Nair's interests?
Ashwin Harikumar Nair has interest in Social Services, Education, Environment, Science And Technology, Animal Welfare.
What skills is Ashwin Harikumar Nair known for?
Ashwin Harikumar Nair has skills like Analog Circuit Design, Cadence, Matlab, Python, C++, Verilog, Pcb Design, Lt Spice, Vlsi, Simulink, Mixed Signal, Multis.
Who are Ashwin Harikumar Nair's colleagues?
Ashwin Harikumar Nair's colleagues are Miya Gong, Himanshu Bhalla, Surbhi Shapara, Dennis Sanders, Mei Har W., Dallin Wheeler, Mark Gardner.
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