Analog/Mixed Signal Designer with over 9 years of experience at Intel2019- Now -> Multi GBps clocking circuits for DDR5/LP5 PHY for Intel System-on-Chip (SoC) products.2015-19 -> PLLs/Current Reference generators for intel Atom Cores/5G Modem MPHY2013-15 -> MS Analog Circuits ASU, Intern at High Speed IO Lab Intel (SATA 6G)Hands on Experience with - High Speed Clock Reception, DLL, Distribution, Duty Cycle Correction/Detection, Data path design, Serializers, Clock Splitters, Clock Crossing Circuits, Equalizers and Digital Calibration Loops/FSMsEntire Analog/Mixed Signal Design flow - variation, EMIR analysis, Aging, Mixed Signal Timing - with multiple successful tape out experience on sub 10nm CMOS Finfet (TSMC)
Listed skills include Analog Circuit Design, Cadence, Matlab, Python, and 19 others.