Babken Gyarakyan Email & Phone Number

Armenia

Armenia

Support of noise suppression technologiesMy activities in this areaAndroid - I have expertise in integrating SDKs using Kotlin and Java, with interaction with native CPP (C++).iOS - I am skilled in integrating SDKs using Swift and Objective-C, and I have experience in interacting with native CPP libraries.Web - I have worked with Electron and JavaScript/Node for SDK integration.Furthermore, I have hands-on experience with various frameworks such as WebRTC and Linphone.

Armenia

I have expertise in supporting Memory Built-In Self-Test (BIST) IP technologies and related software tools throughout the entire design process, from RTL generation to integration into user designs, synthesis, Static Timing Analysis, and ultimately reaching the silicon stage.My activities in this area include customer consultancy, management, conducting trainings, handling mail communications, participating in periodic status calls, conducting debug sessions, and providing post-silicon diagnosis. I am also experienced in flow automation to streamline the design process.I am proficient in the following:SDC (Synopsys Design Constraints): I have experience in creating and applying SDCs for design constraints.Synopsys Design Compiler: I am skilled in using Synopsys Design Compiler for synthesis, optimizing RTL designs for timing, area, and power.Synopsys Primetime: I am proficient in using Primetime for Static Timing Analysis (STA) to ensure design timing closure.Spyglass: I have worked with Spyglass for design verification and linting, ensuring adherence to coding guidelines and identifying potential issues.BIST: I have expertise in Memory BIST IP technologies and their integration into user designs.

I have experience in the development, bug fixes, and enhancements of an EDA (Electronic Design Automation) tool. The tool primarily focuses on Timing (SDC), Constraint verification, and ensuring alignment between SDC and RTL. Additionally, I have worked on Constraint generation and budgeting, and System Verilog Assertion generation.In terms of skills, I am proficient in the following:Verific: I have experience with Verific, a library used for parsing, analyzing, and manipulating hardware design descriptions.Qt: I am skilled in using Qt, a cross-platform application framework, for developing user-friendly and efficient graphical user interfaces (GUIs).VHDL: I have expertise in VHDL (VHSIC Hardware Description Language), a hardware description language used for digital circuit design.C++: I am proficient in C++, a versatile programming language widely used in software development, including EDA tools.Verilog: I have worked with Verilog, a hardware description language used for modeling and simulating digital systems.

development, bug fixes, enhancements of EDA tooltool was focused on Timing (SDC),

Support of BIST verilog IP-s and toolchains related to them.

Click to edit position descriptionSupport of BIST verilog IP-s and toolchains related to them

Yerevan

Simulation environment setup / debugging with various tools:* Creation of automation setup / debugging with various tools;* Debugging of simulation failures with Aldec, NCSim and ModelSim;* Bug reporting and verification.Automation for Regressions results calculation/reporting:* A various scripts creation with Python( confluence API, Network API, etc.);* Scripts(Bash, Python) to check the validness of testing;* Python scripts to automate testing of FPGA compiler tool installation/final verification of remote hosts(different version of OS)/VM, etc.);* Python scripts to collect all regression results and fill them in to the confluence page.* Automation scripts and environment creation;* Experiments with RTL/TB (in Verilog) to simplify the case and localize the issue.Technologies/Languages/Tools:Python, TCL, Verilog, Aldec Riviera, proprietary FPGA compiler

Yerevan

Development of mapping project for transforming the LLVM-assembly code (Intermediate representation of LLVM) into AST (Abstract Syntax Tree) generated by Open64 compiler frontend (called WHIRL tree):1. Front-end creation2. IR lowering3. Code back generation4. Optimizations on IR5. Assembly code generation

Master'S Degree, Cosmology

Bachelor'S Degree, Laser And Optical Engineering