Benjamin C. Email & Phone Number

Santa Clara, Ca

- Verifying power management features for high-performance CPU cores- Verification architect for power management IPs for CPU/GPU/SOC- Execution lead in verifying power management IPsPower/Performance Verification Lead- Power/Performance Metrics Modeling for battery life improvements- Design power/performance simulation platform with external battery-life-sensitives benchmarks- Establish synthesizable verification components to measure power/performance metrics periodically- Develop power/performance models for early design tradeoffsCPU Cores Post-Silicon Validation Lead- System/Lab/Inventory Management- Silicon Validation from tape out to production- Silicon Debug, Triage and Root CauseStructural Verification Lead- CDC Verification- Low Power Verification- Gate Level SimulationFormal Verification Lead- Formal Property Verification- Data Path Formal Verification- Formal Verification Methodology and Infrastructure

Responsible for ATPG modeling and verification of custom circuits across all AMD projects. This position includes extensively interacting with internal circuit design groups, ATPG groups and external ATPG vendors. Achievements include co-found the global ATPG modeling and verification group along with DFT Center of Expertise (COE), establish the first AMD ATPG modeling guidelines for customized circuits, etc.Winner of AMD "Above and Beyond" award for successful formation of the 1st One-AMD ATPG custom circuits modeling requirement specification

San Jose, Ca

In-house Memory BIST design;MBIST IP insertion and validation;Memory Failure Analysis on silicon;

Asynchonous Transfer Mode (ATM) product R & Asynchonous Transfer Mode (ATM) product R &

Master'S Degree, Electrical And Computer Engineering (Ece)

Bachelor'S Degree, Computer Science