Bill Chen Email & Phone Number

Zhangjiang, Pudong, Shanghai, Prc

digital IC front-end design, code systemverilog design on schedule, with Lint rule/cross-clock domain issue clean, design synthesizable check and DFT test friendly.macro verification on Unit and system level, based on VMM/MVM methodology, including macro development plan, testbench plan, function and code coverage analysis and bug tracing.perl/shell/TCL script development to speed-up design coding and improve design/verification qualityFPGA verification, including design compile/synthesis/PnR on Xilinx platform and verilog/assemble/C test cases creation.

digital IC design/verification for SOC. mentor Junior designers to complete design/verification on schedule.

digital design/verification for SOC.

Master, Integrated Circuit Engineering

analog/digital design, test and manufacture

Bachelor, Electronic Engineering