Bimal Patel Email & Phone Number

Mississauga, On, Ca

Mississauga, On, Ca

Mississauga, On

Motivate, schedule and support PHY IP digital design, customer package development, digital and mixed-signal verification across 3 sites. Enable customers by delivering first-time-right PHY IP that supports protocols such as PCI Express, SATA, USB and Ethernet

Leading SERDES PHY verification • Prioritizing feature verification and coverage cases• Conducting code and waveform reviews• Focusing on successful tapeouts and customer deliveries• Tracking actions and following-up to closure• Verification council chairFocusing improving the process and results for:• Regression results• Code and functional coverage• Bug curvesBuilt a Serdes PHY team in Hyderabad, India over a 7 year period• Focused building a self-sufficient and equivalent team• Started with 2 engineers and now have a team of 28• The team now owns design, firmware and verification responsibilities

Implemented SystemVerilog assertions, constraints, functional coverage bins, scenario generators and testcases for PCI Express Gen1/2/3 PHY. Designed and Verified HDMI Tx PHY digital block. Achieved 1st time success.

• Technical Lead for HDMI (High-Definition Multimedia Interface) receiver digital core. • Managed five designers to deliver versatile and verified silicon result.• Delivered architecture definition, area, schedule and status updates.• Specified verification environment to allow full feature list test coverage.• Designed HDMI decode and HDCP (High-bandwidth Digital Content Protection) v1.1 decryption blocks.• Defined RGB <-> YCbCr colour-space conversation, YCbCr 422 <-> 444 up/down conversion blocks.• Detailed prototype and characterization effort.• Interfaced with production test team to meet test time and coverage targets.• Regularly interfaced with analog team produce several analog-interface control blocks.• Improved design, verification and compliance methodology.• Designed and verified DDR2 SDRAM memory interface block using DDR2 controller IP core.

Designed a DVI receiver and an HDMI-like receiver.

- Designed full-custom circuits for DSPs used in wireless infrastructure applications.- Full-custom circuit design of the DSP16210 external memory interface.- Optimized the architecture for size, power and speed.- - Implemented full-custom Booth-Encoded multiplier, three input carry-skip split-adder, two input carry-skip split adder/subtractor, register units and bit-manipulation unit.- Implemented and tested synthesized 0.18m m 200 MHz DSP16410B core data path.- Designed arithmetic units using Module Compiler (MCL).- Wrote the VHDL for the arithmetic and register control units and synthesized them using Synopsys.- Conducted HSpice simulations of top-level clocks and busses.- Conducted experiments on the IDS and FIB machines to isolate a process issue.- Designed 768K internal SRAM with Redundancy and the memory interface to the split-transaction bus for the 0.16m m 250MHz tri-core StarPro project.

Designed a double-port, double-clock SRAM full-custom layout using HSpice simulation and Cadence layout tools.

Meng, Electrical Engineering

Computer Architecture, Wireless Communications and Network Systems.

Basc, Electrical Engineering

VLSI, Digital and Software Systems (project: C++ Real-Time Operating System).