Brian Kaether Email & Phone Number

Sunnyvale, California, United States

Pasadena, California, United States

Pasadena, California, United States

Designed and tested an entire block of the ASIC independently. The job of this block was to constantly poll different sensors on the chip and "wake up" the main system processor out of low power mode upon certain conditions.Tests were written at both the block and full chip level.Achieved 100% code, branch, assertion, and FSM coverage on this block using Cadence Integrated Metrics Center.Designed and tested a synthesizable driver for the UMC 55nm embedded flash IP independently. The driver was responsible for manipulating various signals under precise timing constraints in order to successfully perform operations such as power-up, configuration, reading, writing, sector erasing, and chip erasing.Tests were written at both the block and full chip level.The driver also managed redundancy sectors, allowing for increased yield at tape-out.Worked in a team of two to dramatically improve flash memory performance by integrating both the ARM Corelink CG092 AHB Flash Cache and ARM Corelink GFC-100 Generic Flash Controller into the system.Created a behavioral flash model to allow system tests to be run successfully in Verilator, in addition to Xcelium.

Stanford, California, United States

West Harrison, New York

Master Of Science - Ms, Electrical Engineering

Bachelor Of Science - Bs, Electrical Engineering