Led the optimization of Global Engineering strategy, aligning solutions development models across U.S., Asia, and Europe.• Achieved over $600k in operational expense reduction in the first 2 quarters.• Improved time-to-market schedules by 40% and decreased per project NRE costs by $1.5M.

Directed End-End Si management and Roadmap ownership of 10 DT SoC’s (Box + Tray), six chipsets, and five Workstation SoC’s + Chipsets. General Management responsibilities included PnL optimization, leading customer alignment and engagement across all lines of business, Operational planning, and PLC decision owner.

Managed a team of 70+ Architects responsible for the PnP Modeling, Analysis, and Performance KPI’s of 10 Datacenter SoC’s and three Functional IP domains. Created and maintained PLC operational excellence KPI’s and cross-division OKR’s with key stakeholders.

Established a Global Platform Engineering team for Intel’s newly acquired Programmable Solutions Group responsible for delivering internal validation vehicles, broad enabling customer collateral (IoT, Autonomous Vehicle Solutions, AI Training and Inference engines) and Branded Board solutions for a diverse market portfolio – resulting in the delivery of 8 devices in less than 13 months.

Grounds up, systems team creation for industry leading Form Factor Reference Designs (FFRD) and broad enabling system technology. Created and launched a new industry-leading form-factor adopted by all MNC’s and Channel partners.

Global HW Engineering manager which began as the Validation Engineering Manager and quickly transitioned into all of Platform Engineering with a group of 240 engineers and technicians. This organization was responsible for internal and ODM co-developed products for MNC OEM’s and the global Channel market. Co-invented the NUC PC resulting in >$500M in incremental revenue and the creation of multiple new business partners.

The first seven years in Validation, Design, and Architecture, stabling the foundation of teamwork and network building, business acumen, the importance of process that does not encumber innovation, and proactive, continuous efficiency improvements.Led design development activities for both Desktop product and Reference Validation designs. Architected and designed solutions for back-plane I/O, Graphics, power delivery, Memory, and other CORE related subsystem interfaces. Mentored both… Show more The first seven years in Validation, Design, and Architecture, stabling the foundation of teamwork and network building, business acumen, the importance of process that does not encumber innovation, and proactive, continuous efficiency improvements.Led design development activities for both Desktop product and Reference Validation designs. Architected and designed solutions for back-plane I/O, Graphics, power delivery, Memory, and other CORE related subsystem interfaces. Mentored both RCG's and Design Engineer's within Desktop and Server Platform development teams. Show less