Brian Schuh Email and Phone Number

Developed System-on-Chip solutions for High Performance ComputingCollaborated with 3rd party IP developers, evaluate technical optionsCreated proposals for funding campaign

Managed ThunderX4 ARM Server Memory Subsystem Team for HPC and Cloud applicationsLed development of Coherent Mesh Interconnect, L3 Cache, DDR/HBM memory interfacesDrove top level SOC and optimization of Architecture, Physical Design, Package/PlatformEvaluated 3rd party IP (Serdes, DDR, HBM, PCI) and drove collaboration on custom enhancementsInterfaced with HPC customer for Design/IP definition and development activities to meet contract milestones

Managed High Speed IO Development team for Qualcomm Datacenter TechnologiesDeveloped custom mixed signal proprietary Serdes and SOC clocking IP for TSMC 7nmManaged CPU custom circuit and Signal/Power Integrity teamsResponsible for 3rd party IP selection and development execution Delivered IP and led hardware bring-up for 7nm ARM server SOC

Created High Speed Serdes team developing proprietary IP for Qualcomm Datacenter TechnologiesLed development and characterization of 10nm and 7nm IP test chipsManaged NIC development, Advanced Technology team and SOC Performance modelingDelivered DDR memory Compression IP on industry first 10nm Server SOC, Centriq 2400

High Speed Serial Link DevelopmentDeveloped Industry Standard and Proprietary Serdes IP up to 20Gb/sDelivered IP into IBM ASIC Roadmap for seven technology generationsDelivered IP into IBM Server ASICs and Power8 processorManaged analog, logic, layout design and lab characterization skills