Integrating various semiconductor device processes including Si, GaAs, InP, GaN and passives for high yield micro transfer printing to host microsystems.

Developed and continually improved Quality Management System (QMS) to comply with stringent Aerospace AS9100 and ISO9001 standards. Focused on improving Corrective and Preventative Action (CAPA) system, supplier performance monitoring, customer requirements verification, auditing, key metrics and management reviews. Improved product quality for flight bound electronic systems by spreading Six Sigma methodology throughout organization. Created detailed Process Maps and FMEAs of PolyStrata processes. Managed customer and supplier interaction regarding quality systems and issue resolution. Developed capacity and cost software tools used for proposal planning and cost estimates. Wrote visual basic scripts to port RF tests into relational database. Analyzed and presented production data and experimental results using JMP software.Assisted technology transfer, planning, equipment acquisition, installation, process development, documentation, hiring and training for new Durham manufacturing site. Demonstrated improved product reliability by introducing HiPOT device testing to screen intermittent short defects.Developed sub-mm thick UV-LIGA mold masking processes for NiCo alloy MEM's process to meet and surpass customer requirements. Demonstrated significant cycle time and yield improvement using spray liftoff technology.

Developed next generation NRF2 GaN HEMT devices delivering 20:1 VSWR compliance at 48V operation. Successfully performed and analyzed Highly Accelerated Life Test (HALT) to determine Activation Energy and MTTF estimate for power degradation.Technical Project Team lead with monthly status reviews by the CEO to outsource wafer fabrication processes to west coast partner. Responded to unexpected excursions by analyzing qualification data and designing experiments to determine root cause and countermeasure. Summarized efforts and presented 2012 CSmantech paper.

Matured GaN on Silicon processes for manufacturability boosting rolled throughput yield from 12 to 65%. Emphasis on PECVD deposition, ICP etch, and electroplating. Improved passivation film stoichiometry and stress control to reduce device leakage current. Improved gate etch endpoint signal intensity to reduce critical dimension variation. Improved up-time stability of plating line by controlling rate as a function of bath age.Led and resolved two business critical projects: drain leakage and schottky defect reduction. Identified and eliminated several sources of chlorine contamination causing nickel corrosion improving device reliability.

Developed high voltage field plate manufacturing controls to improve performance and yield. Developed and qualified wafer level hermetic glassivation process. Led project to qualified multiple substrate suppliers. Saved $3M thru Six Sigma Initiatives in wafer fab.

Responsible for plasma etch and backside metallization.

Ported R&D processes to new 3 inch GaAs pilot production fab. Received Divisional achievement award for qualifying in-house built capless implant anneal process.

Responsible for Al/TiW/Ti Plasma etch. Reduced dry metal etch defect density 6X improving yield due reduction of shorts.