Bruce Bateman Email & Phone Number

Fremont, CA, US

Fremont, California

I’ve taken the last year off to stay at home to help my wife through a couple of surgeries to improve her health and lifestyle. This included double knee replacement surgery. She is now well into recovery, so I am now looking for a new and exciting opportunity.

San Jose, California

TC Lab is a startup venture developing an approach to the manufacture of thyristor-based 3-dimensional memory array as a low cost alternative to SRAM and DRAM. I was one of the 5 founders of the company. My responsibilities were (1) using Proprietary TCAD to develop, simulate and characterize memory cell and memory array structures across wide process.

Santa Clara, California

Development and design of OTP Anti-Fuse Memory and new alternative SRAM/DRAM memory approaches. Includes TCAD bitcell development, Spice bit-cell-model development, cell array architecture and operation, design of programming circuits, sensing circuits, support circuitry, IP block architecture, and logic.

Sunnyvale, CA

• Key Contributor on Metal-Oxide RAM development. Flawlessly designed/taped-out two fully functional RRAM test chips, one consisting of device modules and decoded 1T1R arrays, and the other being a 256kb macro with state.
• Developed techniques controlling program/erase currents in the memory cell in the area of resistive memory, and facilitated the integration of Unity technology and IP into Rambus after the acquisition.
• Taped out a fully functional 256K-bit 1T-1R RRAM memory test chip on a minimally supported CMOS foundry process, and solved masking/stepper compatibility issues between the foundry and labs.

Sunnyvale, CA

• Managed chip design, CAD and IT groups in addition to acting as an individual contributor in design and CAD efforts. Guided the development of memory circuit and chip architectures to provide chip performance and.
• Collaborated with device and process groups on the analysis and development of the CMOx memory device and processes.
• Prepared and presented materials for investors, technical partners, and prospective technical partners regarding the technology, chip design and product capabilities.
• Assisted in facilitating the sale of the company to Rambus via technical presentations and interaction with key Rambus staff.

Milpitas, CA

• Supervised design staff and acted as an individual contributor on the design of technology development test-chips and commercial grade stand-alone SDR Synchronous SRAM chips utilizing T-RAM’s proprietary.
• Utilized 45nm bulk-CMOS for a TCAM memory cell using a single thyristor storage element.

Santa Clara, CA

Mountain View, CA