Lead validation designer of full-chip test environment for Intel Optane Next Generation Memory. Using testing framework UVM with a coverage model to drive a digital simulation environment. Designing a dynamic test environment across C++, Python, and Systemverilog for multilevel testing.Key Accomplishments:- Improving integration test performance by over 20% and reduced memory usage by 15%- Refactoring major unit test bench to greatly reduce debugging and new feature validation time- Integrating PCIe IP's for key co-simulation test bench environment

Led group in a proof of concept AI project using TensorFlow with Markov Chains for RF emission prediction. Worked to build a company framework for evaluating and designing machine learning projects.

Worked with the Logic Design and Validation team in the Non-Volatile Memory Solutions Group working on Next Generation non-volatile memory devices. Utilized the Universal Verification Methodology (UVM) and SystemVerilog to integrate multiple unit level test blocks into the full chip model, developed a methodology for using System Verilog Assertion macros in RTL design, and created a UVM clock calibration validation design.

Designing an efficient reduction-free multiplication for finite fields and polynomial rings. Using Verilog HDL to create hardware that will asses the algorithm presented by the research paper. This will be tested and analyzed to show the efficiency of the new design, then I will document the hardware design and results.

• Designed lab structure to reinforce and give hands-on experience to topics discussed in lecture• Lectured on topics important to Data Structure and algorithm design including stacks, queues, searching, and sorting• Introduced students to version control systems, programming on integrated development environments, debugging techniques, and test-driven development with Gtest