Craig Hanson Email & Phone Number

International Falls, Mn, Us

International Falls, Mn, Us

Charlotte, North Carolina, Us

I work on the approval of complex airborne electronic hardware designs (ASIC/SoC/FPGA) relative to DO-254/FAA/EASA guidance as delegated by Honeywell under their partnership for safety plan with the FAA. My company delegation title is TSO Specialist which is most similar to company DER in industry verbiage. I am currently delegated to aprove DAL A level AEH from my experience in authorized areas including Guidance & Navigation/Inertial Systems, APU, Communications, Flight Controls, Instruments, Air Data, Warning Systems, Flight Data, Lighting, and Passenger Entertainment. I additionally have experience on turbofan engine ECU compliance finding.

I was responsible for defining the needed subsystem verification to both build on top of and leverage the multiple block level verification efforts. This required defining the role of a subsystem level of verification in a new interconnect/memory subsystem development effort. Additionally, I built the subsystem verification team from the ground up during the course of this development period.Some highlights: - Developed Subsystem Verification Specification (Architecture of verif tb/env, high level test plan, and alignment with multiple block and full chip verif entities)- Work flow estimating and planning over complete project lifespan- Hiring and managing of new full time and contract employees to execute on the subsystem - Key contributor to implementation of continuous integration methodology across design/verif ICM database (defining needed smoke testing at the different levels while trying to minimize overhead of time to submit, workflow issues with shadow branch integrations to live, and tool definition/usage)- Championed multiple cross domain efforts to bring alignment and reduce duplicate work efforts across architecture, integration, design, verif, physical design and software. (chip wide instance naming alignment and use, new uses of executable specs starting at architecture through verif and software for chip configuration space definition and instance name usage)

I was responsible for the DRAM memory subsystem in an enterprise class line of ARM based SoC's. This included memory controller and DRAM PHY logic evaluation/performance evaluation/enterprise grade feature definition and implementation. This work focused on DDR3 and DDR4.Some notable recent work included:- RAS feature definition from the perspective of the DRAM subsystem- SoC DRAM Subsystem and DRAM Power monitoring/throttling feature and working definition completed- Analyzed the memory subsystem in a C-level performance modeling environment for architectural performance investigationsAdditionally, I executed on the following tasks:- Directed the DRAM memory subsystem design verification effort from its high risk long pole position to a back on schedule on-time tape out position with high coverage.- Wrote the firmware boot loader code to initialize and train the memory controller, DRAM PHY, and DDR3/4 memory populated. This was inclusive across multiple DRAM channels of any legal population of up to 2 DIMMs per channel. This was also fully optimized for performance based upon the chosen populated DIMMs. Additionally, the memory controller performance was programmed to be optimized based upon the system address to physical DRAM address translation relative to expected enterprise traffic loads.- Championed and worked to define a not yet fully implemented shared RTL verification/Silicon validation environment to leverage the performance optimized boot loader firmware code in conjunction with the powerful UVM assertion verification environment. This was going to combine duplicated error prone workload across teams to produce a much more efficient team debug environment between simulation efforts and lab efforts with repeatability in both directions.- Defined and assisted RTL implementation of a DRAM BIST solution utilizing a standard RAM BIST engine. This was implemented at the DFI interface.- Wrote the memory controller silicon validation test plan.

Boise, Idaho, Us

Logic Design, System Development, Xilinx FPGA Design/Prototyping, Altera FPGA Design/Prototyping, Simulation Modeling/Environment(Modelsim), Synthesis(Synopsys/Synplicity/Altera) and Hands-On Lab Characterization/Debug.