Drove the RTL definition of the Global Clock network for Intel’s newest CPU architecture which included defining all the RTL macros that the design team would utilize to create a multi-depth clock-gating network. Owned the Clock and IO definitions for the CPU, and was the primary CDC / RDC owner for the program. Performed HSPICE simulations to optimize stdcell selection for driving clocks on front-side as well as Intel's new back-side metal layer stacks. Collaborated with other Clock engineers to define the H-tree and Mesh networks to arrive at a Global Clock design that was optimized for power and performance (PPA), jitter, duty-cycle and skew.

Managed a team of RTL, Validation, Circuit Design and Structural Designers to deliver mixed-signal solutions into PCHs, 5G Baseband Processing Units and later into the Intel Optane Memory product

RTL designer working on Integrated Clock designs: integrating PLL and other IPs into a super-IP for delivery into PCH and Micro-server designs. Gained experience in System Verilog coding, along with all the tools associated with this responsibility (Verdi, VCS, Lintra, GLS, CDC/RDC). Branched out to learn about unit-level (ULT) validation and synthesis and post-silicon debug - in order to create better designs.

Viewplus Technologies creates Braille printers primarily for the use of blind students and professionals. Created the schematic and board layout which connected to an HP inkjet printer to create the first "Emprint" printer which could print inkjet text or images along with embossing Braille (or adding texture to pictures).Also created the FPGA firmware using the Altera Quartus II software (with NIOS processor), and wrote the low-level sub-routines to control the stepper motors, solenoid punches, USB, etc of the board.