Casey Mccoy Email & Phone Number

San Jose, Ca

Support customers with the use of Microchip/Atmel aerospace (rad-hard & rad-tol) ICs (primarily ARM & AVR microcontrollers) and respective development kits.

San Jose, Ca

Physical ASIC design flow (ASIC, FPGA->ASIC, com/ind/mil/aero): Synthesis (Leonardo, Synopsys, PKS); scan insertion (DFTAdvisor, FastScan); clock tree synthesis (CTGen); floorplanning; package selection, bonding; power consumption/ dissipation; simulation (ModelSim for VHDL, Verilog, QuickSim for EDIF, Viewlogic for Xilinx/Altera/Actel); ATPG (FlexTest); fault grade (QuickFault); place & route (Cadence); timing analysis (Primetime); post-layout timing closure; hold logic/design reviews with customers.

VHDL design of 32- and 64-bit memory interface modules in graphics ASICs for S3 Virge ASICs; modules interfaced between master control unit and memories. Testbench development, IKOS hardware-accelerated verification. Perl and C programming for C-model design verification.

Physical ASIC design for FPGA-to-ASIC: synthesis (Galileo); clock tree synthesis; test structure insertion; I/O selection, insertion; package bonding; power estimation; simulation (QuickSim for EDIF, Viewlogic for Xilinx/Altera/Actel); ATPG (FlexTest); fault grading; place & route; post-layout timing closure. Perl and C coding to supplement design flow.

Design with FPGA; analog/digital board design for conditioning analog signals, sample/hold and A/D conversion. Designed FPGA logic, interfacing with 68000 processor. Board/system design, place & route; application debug.

Analog and digital design (with A/D, D/A) of interface boards for digital tester and DUTs. C coding and scripts for batch runs; preparation of mil-std supporting docs. Secret clearance.

Ms, Electrical Engineering

Bs, Electrical Engineering