Chan Lim
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Chan Lim Email & Phone Number

3D NAND Device and Reliability, Chip Analysis Muti-team Leader, PM, Research Fellow at SK hynix
Location: San Jose, California, United States 5 work roles 2 schools
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Role
3D NAND Device and Reliability, Chip Analysis Muti-team Leader, PM, Research Fellow
Location
San Jose, California, United States
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Who is Chan Lim? Overview

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Quick answer

Chan Lim is listed as 3D NAND Device and Reliability, Chip Analysis Muti-team Leader, PM, Research Fellow at SK hynix, a with 7465 employees, based in San Jose, California, United States. AeroLeads shows a matched LinkedIn profile for Chan Lim.

Chan Lim previously worked as 3D NAND Device/Reliability, Chip Analysis Muti-team Leader, PM, Research Fellow at Sk Hynix and Senior Staff Engineer at Intel. Chan Lim holds Master'S Degree, Physics from Yonsei University.

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SK hynix

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Profile bio

About Chan Lim

Chan Lim is a 3D NAND Device and Reliability, Chip Analysis Muti-team Leader, PM, Research Fellow at SK hynix.

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Chan Lim's current company

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SK hynix
Sk Hynix
3D NAND Device and Reliability, Chip Analysis Muti-team Leader, PM, Research Fellow
San Jose, CA, US
Website
Employees
7465
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5 roles

Chan Lim work experience

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3D Nand Device And Reliability, Chip Analysis Muti-Team Leader, Pm, Research Fellow

San Jose, Ca, Us

3D Nand Device/Reliability, Chip Analysis Muti-Team Leader, Pm, Research Fellow

Current

Icheon, South Korea

Aug 2011 - Present

Senior Staff Engineer

San Jose, California, United States

1. Nov. 2007 ~ June 2011- Senior Tachnical Staff- 2D NAND Flash Cell Integration / Intel, Santa Clara, CA (NAND Cell Dielectric Development for NAND Cell Integration in Intel-Micron JDP)- 2D NAND Planar High-k IPD/Metal FG Cell Reliability Improvement- 2D FG NAND Cell Electrical Analysis / Yield Analysis - 2D FG NAND Cell & Midsection Intergration 2. July 2004 ~ Oct. 2007 - Tachnical Staff- Thin Film/Diffusion in Advanced Module Technology Development Dept for NOR Flash /Intel, Santa Clara, CA- Deep Contact Silicide Development, - high-k/ALD oxide IPD Development- Diffusion/CVD Process (Poly, Oxide, Nitride) Development

Aug 2004 - Jul 2011

Senior Staff Engineer

New York, United States

- Senior Staff Engineer / Infineon-IBM JDP (called IBM alliance with other companies) - ON Gate Stack, High-k/Metal Gate development for Logic Transistor/ In

Feb 2003 - Jul 2004

Project Engineering

Icheon, Gyeonggi, South Korea

1. 2001 ~ 2002- Senoir Staff Engineer / International Sematech Hynix assignn - Logic High-k & ON Gate Stack Engineering for advanced Logic Transistor (ON, High-k Gate Dielectric Development, Transistor Characterization) 2. 1991 ~ 2000- Senior Staff Engineer / DRAM Capacitor Module Intergration Leader - DRAM Capacitor Integration - DRAM Cell Dielectric Development (ON, High-k, DRAM Capacitor Electrical Characterrization) - Diffusion / CVD Process Development ( Doped Poly, HSG, HTO oxide, ALD )

Aug 1991 - Jan 2003
Team & coworkers

Colleagues at SK hynix

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2 education records

Chan Lim education

FAQ

Frequently asked questions about Chan Lim

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What company does Chan Lim work for?

Chan Lim works for SK hynix.

What is Chan Lim's role at SK hynix?

Chan Lim is listed as 3D NAND Device and Reliability, Chip Analysis Muti-team Leader, PM, Research Fellow at SK hynix.

Where is Chan Lim based?

Chan Lim is based in San Jose, California, United States while working with SK hynix.

What companies has Chan Lim worked for?

Chan Lim has worked for Sk Hynix, Intel, Infineon Technologies, and Hyundai Electronics Industries Co., Ltd..

Who are Chan Lim's colleagues at SK hynix?

Chan Lim's colleagues at SK hynix include Eui Jong Shin, Doori Kim, Chulmin Sun, Minjae Koo, and Francis Son.

How can I contact Chan Lim?

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What schools did Chan Lim attend?

Chan Lim holds Master'S Degree, Physics from Yonsei University.

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