As a Verification Engineer II, I worked in GLS verification, and clock/reset generation across high-performance, robust systems. My role involves in-depth verification from Pre-GLS to Post-GLS stages, with extensive experience debugging SDF violations and developing efficient methodologies for default value verification. Also involved vector verification (post silicon) and made script automation.

Worked on developing the new methodologies. Create Gate level simulation environment from scratch and debug several scenarios. Also involved in power analysis runs. GLS verification activities, including Pre-GLS, Post-GLS, and PAGLS setup and debugging. Developed power management timing windows using GLS FSDBs to optimize power across designs. Overseeing verification of ARM processors with a focus on regression checks and individual block testing, ensuring functional and performance standards are met. Developed and executed test cases for major releases related to the Amba protocol, while ensuring connectivity and default value verification for registers and memories through EMA. Also worked in script automation.

Trained on Design and Verification. Also hands on Verilog, System verilog, UVM Methodology and protocol knowledge.