Worked mainly on front end design for a Virtio processor. Basically a proxy block with a very complex algorithm. Did two versions of the design to enable more features and increased performance . Additional front end design duties and support.

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Was asked to come on board and help pull in the development of the SOC (SSD controller).Played a critical role in achieving the tapeout of this device. Took over many duties that were in trouble and needed special focus and understanding.Helped to lead the development of the new flow with DCG synthesis and prove that DC physical would achieve a much cleaner hand off to layout group. With more predictable results. Flew to Taiwan to ensure this hand off went smoothly. • Optimized Verilog (RTL) design work for timing closure.• Integration of Arteris’ NOC tool generated AXI switch fabric • Verification of items above • Synthesis/LEC/STA/Lint

Working on Entropic's latest dCSS (Digital Channel Stacking Switch) • Digital verilog/vhdl RTL design work.• DSP type RTL structures (FIR, FFT etc) • Verification• Synthesis

Rejoined Solarflare in May 2011.Contributing to the new Solarflare controller ASIC code named "farmington"Taped out to TSMC (40nm) Dec 17th 2012• Digital verilog RTL design work. • Static Timing• Back End eco fixing • Verification

• Verilog/VHDL rtl design work of DSP / image processing applications. Specifically FIR filters, DeBayer algorithms, Color conversion and pipeline management. • C-Model verification and comparison of the above RTL Using ncsim tools. • FPGA work with both Xilinix and Altera based parts.

• Digital verilog RTL design work • FPGA verilog design work using Altera devices and Quartus software • Top level static timing • Limited Synopsys ICC experience • Primerail, Primetime, DC, VCS, Spyglass lint, Conformal LEC.• Top level static timing using Primetime SI. • Provided support to synopsys ICC engineers.• Lab board/chip/FPGA initial bring-up and validation.• Helped set up flows and scripts for engineers to follow for Compilation, Simulation, Synthesis.

• Lead digital designer of chip, a 92M Transistor 40x40 SONET Time Slot Interchange (TSI) device in TSMC 0.13mm technology.• Set up flows and scripts for junior engineers to follow for Compilation, Simulation, Synthesis, and ATPG.• Designed two key blocks, transmit (Tx) and receive (Rx) interfaces. Key challenges were:o Elastic Store and Framer on Receive blocko Overhead add/drop features in both Rx and Tx blockso Took both blocks through design, verification, synthesis, APR (magma), and verification.• Both blocks had first-time design success! Increased functionality added to later-generation devices without incident.• Led top-level verification effort.. • Top Level Auto Place and Route using Magma. • All top level static timing using Primetime SI. • Led test-vector generation effort,using a novel method to do scan testing easily.• Provided back-end test support to Product/Test engineering.• Lab board/chip validation.

§ Design rtl (VHDL) work on MDIO & I2C logic, timesliced DS2/DS3 framer architecture, clock difference detection logic, timesliced T1/E1 framer architecture, T1 framer protocol logic, Transmit DMA Controller and 100BaseT protocol logic. § Specification of 84 serial data stream to 8 bit parallel data bus sub block.§ Specification of 8 bit parallel data bus to 84 serial data stream sub block.§ Designed custom VHDL testbench architecture and simulation suite.§ Simulations of both RTL and Gate netlists with Cadence NCSIM.§ Synthesis to 0.18, 0.25, 0.35 Micron libraries using Synopsys tools.§ Scan insertion via Mentor DFTA tools.§ Test Vector generation and re-simulation.§ Schematic revisions using Compass tools.§ Schematic conversions to VHDL using Cadence Composer.